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ics for communications framing and line interface component for pcm 30 and pcm 24 falc54 peb 2254 version 1.3 data sheet 11.96 t2254-xv13-d1-7600
edition 11.96 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen siemens ag 1996. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. peb 2254 revision history: current version: 11.96 previous version: 04.96 page (in previous version) page (in current version) subjects (major changes since last revision) C 52, 53, 108 extended crc4 to non-crc4 interworking C 42, 108 selected cmi precoding C 102, 251 receive/transmit timeslot offset shift in steps of each sclkr/x (8 mhz) cycles 69, 70, 218, 219 70, 71, 216, 217 calculation of receive/transmit timeslot offset programming C 87, 236 status change interrupt capability C 113, 261 loss of signal recovery conditions C 55, 108, 132, 133 sa6 bit detection according to ets 300233 C 17, 108 enable cas freeze output C 187, 188, 268, 281 receive pulse density detection 143 141 400 msec time out available in all multiframe formats 296, 300, 303, 307-312, 314 289, 293, 296, 300-305, 307 electrical specification 145, 293 143, 286 version status register
peb 2254 table of contents page semiconductor group 3 11.96 falc54 in pcm 30 mode 1 general features e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin configuration of falc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 general functions and device architecture e1 . . . . . . . . . . . . . . . . . . . 31 2.1 functional description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.1 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.2 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.1.3 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.1.4 operating modes e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1.4.1 doubleframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1.4.2 crc-multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.4.3 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.2 signaling controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.2.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.2.2 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.2.3 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.4 time-slot assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.2.5 s a bit access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.2.6 interface to system internal highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3 operational description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.1 detailed register description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.1.1 control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.1.2 status register address arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
peb 2254 table of contents page semiconductor group 4 11.96 falc54 in pcm 24 mode 4 general features t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.1 pin configuration of falc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.2 pin definitions and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.5 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.6 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5 general functions and device architecture t1 . . . . . . . . . . . . . . . . . . 172 5.1 functional description t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.1.1 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.1.2 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.1.3 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.1.4 operating modes t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.1.4.1 4-frame multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.1.4.2 12-frame multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.1.4.3 extended superframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.1.4.4 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.2 signaling controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 5.2.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 5.2.2 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 5.2.3 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.2.4 time-slot assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 5.2.5 bit oriented message mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.2.6 4 kbit/s data link access in f72 format . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.2.7 interface to system internal highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6 operational description t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.1 detailed register description t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6.1.1 control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6.1.2 status register address arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 7 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 7.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 7.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.4 recommended oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 7.5.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 7.5.1.1 siemens/intel bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 7.5.1.2 motorola bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 7.6 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
peb 2254 table of contents page semiconductor group 5 11.96 7.6.1 timing of dual rail and optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . 299 7.7 system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 7.8 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 7.9 jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 7.10 pulse templates - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
semiconductor group 6 11.96 framing and line interface component falc54 peb 2254 cmos p-mqfp-80-1 type version ordering code package peb 2254-h v1.3 q67103-h6813 p-mqfp-80 (smd) falc54 in pcm 30 mode 1 general features e1 line interface ? analog receive and transmit circuitry for e1 signals ? data and clock recovery using an integrated digital phase locked loop ? low transmitter output impedance for a high return loss with reasonable protection resistors ? tri-state function of the analog transmit line outputs ? programmable transmit pulse shape using a minimum number of external components ? jitter specifications of itu-t i.431 and g.703 met ? wander and jitter attenuation/compensation clock smoothing ? dual rail or single rail digital inputs and outputs ? unipolar nrz or cmi for interfacing fibre optical transmission routes ? selectable line codes (hdb3, ami) ? loss of signal indication with programmable thresholds according to itu-t g.775 ? clock generator for jitter free system clocks and transmit clock using an digital phase locked loop ? transmit line monitor ? local loop and remote loop for diagnostic purposes ? only one type of transformer (ratio1: ? 2) for cept 75/120 w and t1 100 w frame aligner ? frame alignment/synthesis for 2048 kbit/s according to itu-t g.704 ? meets newest itu-t rec's, etsi recs. ? programmable formats for doubleframe, crc multiframe ? selectable conditions for loss of frame alignment ? crc4 to non-crc4 interworking of itu-t g. 706 annex b ? error checking via crc4 procedures according to itu-t g. 706
peb 2254 general features e1 semiconductor group 7 11.96 ? performance monitoring 16 bit counter for crc-, framing errors, code violations, error monitoring via e bit and sa6 bit ? insertion and extraction of alarms (ais, remote (yellow) alarm, auxp ) ? idle code insertion for selectable channels ? 8192 khz system clock frequency different for receiver and transmitter ? selectable 2048/4096 kbit/s backplane interface with programmable receive/transmit shifts programmable tri-state function of 4096 kbit/s output via rdo ? two-frame elastic store for receive route clock wander and jitter compensation (can be reduced to one-frame length for master-slave applications); controlled slip capability and slip indication ? flexible transparent modes ? channel loop back, payload loop back capabilities signaling controller ? hdlc controller bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions, programmable preamble ? cas controller ? multiframe synchronization and synthesis itu-t g.732 ? alarm insertion and detection (ais and los in timeslot 16) ? transparent mode ? fifo buffers (64 bytes deep) for efficient transfer of data packets. ? time-slot assignment any combination of time slots selectable for data transfer independent of signaling mode. ? time-slot 0 sa 8-4 bit handling via fifo buffers mp interface ? 8/16 bit microprocessor bus interface (intel or motorola type) ? all registers directly accessible (byte or word access) ? extended interrupt capabilities general ? boundary scan standard ieee 1149.1 ? advanced cmos technology ? p-mqfp-80 package the falcs power consumption is mainly determined by the line length and type of the cable and typical 450 mw.
semiconductor group 8 11.96 peb 2254 general features e1 1.1 pin configuration of falc (top view) figure 1 note: all unused input pins including pin 80 have to be connected to a defined level. p-mqfp-80-1
peb 2254 general features e1 semiconductor group 9 11.96 1.2 pin definitions and functions pin no. symbol input (i) output (o) function 42 48 a0 a6 i address bus these inputs interface with seven bits of the systems address bus to select one of the internal registers for read or write. 4138 3528 2522 d0 d3 d4 d11 d12 d15 i/o data bus bi-directional three-state data lines which interface with the systems data bus. their configuration is controlled by the level of pin dbw: C 8-bit mode (dbw = 0): d0 d7 are active. d8 d15 are in high impedance and have to be connected to v dd or v ss . C 16-bit mode (dbw = 1): d0 d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe/ ble and the selected bus interface mode (via pin im). the unused half is in high impedance. for detailed information, refer to chapter 1.6 . 49 ale i address latch enable a high on this line indicates an address on the external address/data bus. the address information provided on lines a0 a6 is internally latched with the falling edge of ale. this function allows the falc54 to be directly connected to a multiplexed address/data bus. in this case, pins a0 a6 must be externally connected to the data bus pins. in case of demultiplexed mode this pin has to be connected directly to ground or vdd. for detailed information, refer to chapter 1.6 .
semiconductor group 10 11.96 peb 2254 general features e1 pin definitions and function (contd) pin no. symbol input (i) output (o) function 50 rd/ ds i read enable (siemens/intel bus mode) this signal indicates a read operation. when the falc54 is selected via cs the rd signal enables the bus drivers to output data from an internal register addressed via a0 a6 on to data bus. for more information about control/ status register and fifo access in the different bus interface modes refer to chapter 1.6 . data strobe (motorola bus mode) this pin serves as input to control read/write operations. 51 wr/r wi write enable (siemens/intel bus mode) this signal indicates a write operation. when cs is active the falc54 loads an internal register with data provided via the data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 1.6 . read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 52 cs i chip select a low signal selects the falc54 for read/write operations.
peb 2254 general features e1 semiconductor group 11 11.96 54 res i reset a high signal on this pin forces the falc54 into reset state. during reset the falc54 needs active clocks on pins sclkr, sclkx and xtal1 (xtal3 only if xslicer mode selectable by lim1.jatt/rl =10) will be used. during reset C all uni-directional output stages are in high- impedance state, except pins clk16m, clk12m, clk8m, clkx, fsc, xclk and rclk C all bi-directional output stages (data bus) are in high-impedance state if signal rd is high, output xtal2/4 is in high-impedance if input xtal1/3 is high. 53 bhe/ ble i bus high enable (siemens/intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d8 d15). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 1.6 for detailed information. bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 d7). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 1.6 for detailed information. 11 dbw i data bus width (bus interface mode) a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe/ ble. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 12 11.96 peb 2254 general features e1 56 int o/od interrupt request int serves as general interrupt request which may include all interrupt sources. these interrupt sources can be masked via registers imr0 4. interrupt status is reported via registers gis (global interrupt status) and isr0 3. output characteristics (push-pull active low/ high, open drain) are determined by programming the ipc register. 8im i interface mode the level at this pin defines the bus interface mode: a low signal on this input selects the intel interface mode. a high signal on this input selects the motorola interface mode. 1 v ddr i positive power supply for the analog receiver. 2 rl1 rdip roid i i i line receiver 1 analog input from the external transformer. selected if lim1.drs = 0. receive data input positive digital input for received dual rail pcm(+) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive optical interface data unipolar data received from fibre optical interface with 2048 kbit/s. latching of data is done with the falling edge of rclki. input sense is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features e1 semiconductor group 13 11.96 3 refr o reference resistance of 12k 1 % connected to v ss 4 rl2 rdin rclki i i i line receiver 2 analog input from the external transformer. selected if lim1.drs = 0. receive data input negative input for received dual rail pcm(-) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive clock input receive clock input for the optical interface if lim1.drs = 1 and fmr0.rc1/0 = 00. clock frequency: 2048 khz 5 v ssr i power ground supply for analog receiver 6 7 xtal2 xtal1 o i crystal connection 16.384 mhz when an external clock is used, normally if the bit lim0.mas is set, the falc54 functions as a master. 9 10 xtal4 xtal3 o i crystal connection 16.384 mhz a crystal has only to be connected to these pins to generate the transmit clock if xslicer- mode (lim1.jatt=1 and lim1.rl=0) is selected. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 14 11.96 peb 2254 general features e1 13 xl2 xdon o o transmit line 2 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output negative this digital output for transmitted dual rail pcm(-) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. 14 v ssx i ground for analog transmitter pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features e1 semiconductor group 15 11.96 15 xl1 xdop xoid o o o transmit line 1 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output positive this digital output for transmitted dual rail pcm(+) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit optical interface data unipolar data sent to fibre optical interface with 2048 kbit/s which will be clocked off on the positive transitions of xclk. clocking off data in nrz code is done with 100 % duty cycle. data in cmi code are shifted out with 50 % or 100 % duty cycle according to the cmi coding. output sense is selected by bit lim0.xdos (after reset: data are sent active high). the single rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 0. after reset this pin is in a high impedance state until register lim1.drs is set to one. 17 xl1m i transmit line 1 monitor analog input from the external transmit transformer (xl1). this pin must be connected otherwise the xl1 pin could be set in a high impedance state. if digital inputs are selected (lim1.drs = 1) this input has to be switched to v ssx . pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 16 11.96 peb 2254 general features e1 12 xl2m i transmit line 2 monitor analog input from the external transmit transformer (xl2). this pin must be connected otherwise the xl2 pin could be set in a high impedance state. if digital inputs are selected via lim1.drs = 1 this input has to be switched to v ssx . 16 v ddx i positive power supply for analog transmitter 79 xclk fsc o o transmit clock transmit clock frequency: 2048 khz. derived from the sclkx or rclk or internally generated. if lim1.efsc is set high an 8-khz frame synchronization pulse is output via this pin. the synchronization pulse is active high for one 2 mhz cycle (pulse width = 488 ns) and derived from clock supplied by pin xtal1. 80 n.c. not connected. for further application this pin should be connected to v ss . 66 fsc o 8-khz frame synchronization pulse is active low for one 2 mhz cycle (pulse width = 488 ns) and derived from the clock supplied by pin xtal1. 75 clk16m o system clock 16.384 mhz 76 clk12m o system clock 16.384 mhz only if a crystal or an oscillator is connected to xtal3/4. 77 clk8m o system clock 8.192 mhz the frequency is derived from the clock supplied by pin xtal1. 78 clkx o system clock output output frequencies are: 2.048 mhz or 4.096 mhz inverted or non-inverted. the frequency and sense on this pin is selectable via lim0.scl1/0 and is derived from the clock supplied by pin xtal1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features e1 semiconductor group 17 11.96 60 sync i clock synchronization if a clock is detected at the sync pin the falc54 synchronizes to this 2.048 mhz clock. this pin has to be connected to v ss if no clock is supplied. 72 rclk o receive clock extracted from the incoming data pulses clock frequency: 2048 khz if lim0.elos is set, the rclk is set high in case of loss of signal (frs0.los=1). 57 rdo o receive data out received data which is sent to the system internal highway with 4096 kbit/s or 2048 kbit/s (bit fmr1.imod). in 4096 kbit/s mode data is shifted out in that channel phase which is selected by register rc0.sics.the other channel phase is set in tri-state. clocking off data is done with the falling edge of sclkr. the delay between the beginning of time-slot 0 and the initial edge of sclkr (after sypr goes active) is determined by the values of receive time-slot offset rc1.rto5 0, receive clock-slot offset rc0.rco2 0 and rc0.rcos. 71 rfsp o receive frame synchronous pulse (active low) framing pulse derived from the received pcm route signal. during loss of synchronization (bit frs0.lfa), this pulse is suppressed (not influenced during alarm simulation). pulse frequency: 8 khz pulse width: 488 ns setting of fmr3.cfrz the status of the cas synchronizer will be output via this pin. it is set high if the cas controller is in the asynchronous state. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 18 11.96 peb 2254 general features e1 70 dlr o data link bit receive marks the sa8-4 bits within the data stream on rdo. the sa8-4 bit positions in time-slot 0 of every frame not containing the frame alignment signal are selected by register xc0.sa8e-sa4e. 68 xmfb o no function 59 xsigm o transmit signaling marke r marks the transmit time-slots which are defined by register ttr1-4 of every frame transmitted via port xdi. in 4096 kbit/s mode xsigm is active only during the channel phase which is selected by rc0.sics. 65 sypr i synchronous pulse receive defines the beginning of time-slot 0 at system highway port rdo in conjunction with the values of registers rc0.rco, rc1.rto and rc0.rcos. sampling is done with the falling edge of the sclkr clock . pulse cycle: integer multiple of 125 m s. 64 sypx i synchronous pulse transmit defines the beginning of time-slot 0 at system highway port xdi in conjunction with the values of registers xc0.xco, xc1.xto and xc1.xcos. sampling is done with the falling edge of the sclkx clock. pulse cycle: integer multiple of 125 m s. 63 sclkr i system clock receive working clock for the falc54 with a frequency of 8192 khz. 62 sclkx i system clock transmit working clock for the falc54 with a frequency of 8192 khz. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features e1 semiconductor group 19 11.96 55 xdi i transmit data in transmit data received from the system internal highway with 4096 kbit/s or 2048 kbit/s (bit fmr1.imod). latching of data is done with negative transitions of sclkx. in 4096 kbit/s mode data is sampled in the first channel phase if rc0.sics is low. if rc0.sics is high data is sampled in the second channel phase. the delay between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is determined by the values of transmit time-slot offset xc1.xto5 0, transmit clock- slot offset xc0.xco2 0 and xc1.xcos. 69 dlx o data link bit transmit marks the sa8-4 bits within the data stream on xdi. the sa8-4 bit positions in time-slot 0 of every frame not containing the frame alignment signal are selected by register xc0.sa8e- sa4e. 58 rsigm o receive signaling marker marks the time-slots which are defined by register rtr1-4 of every received frame at port rdo. in 4096 kbit/s mode rsigm is active high only during the channel phase which is selected by rc0.sics. 67 rmfb o receive multiframe begin rmfb marks the beginning of every received multiframe (rdo). first bit of the fas word in frame 1 of the multiframe. rmfb is always active high for one 2048 kbit/s period. in 4096 kbit/s mode rmfb is active during the first two bits of the multiframe. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 20 11.96 peb 2254 general features e1 61 xmfs i external transmit multiframe synchronization this port operates as an input for external transmit multiframe synchronization which defines frame 1 of the multiframe on xdi. minimum pulse length is 244 ns. latching is done equivalent to latching data via xdi. the signal has to be issued during frame 1 and has to be reset at least one bit before begin of frame 2. recommended: xmfs begins with the first bit of time-slot 0, frame 1 of xdi. note: a new multiframe position has been settled at least one multiframe after pulse xmfs has been supplied. 27, 37, 74 v ss i power ground supply for digital subcircuits (0 v) for correct operation, all three pins have to be connected to ground. 26, 36, 73 v dd i positive power supply for the digital subcircuits (5 v) for correct operation, all three pins have to be connected to positive power supply. 18 tdi i test data input for boundary scan acc. to ieee std. 1149.1 21 tdo o test data output for boundary scan 19 tms i test mode select for boundary scan 20 tck i test clock for boundary scan pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features e1 semiconductor group 21 11.96 1.3 logic symbol figure 2 falc54 logic symbol
semiconductor group 22 11.96 peb 2254 general features e1 1.4 functional block diagram figure 3 functional block diagram peb 2254
peb 2254 general features e1 semiconductor group 23 11.96 1.5 system integration the figures below show a multiple link application and a nt application. figure 4 multiple link application
semiconductor group 24 11.96 peb 2254 general features e1 figure 5 nt - application 1.6 microprocessor interface the communication between the cpu and the falc54 is done via a set of directly accessible registers. the interface may be configured as siemens/intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers data to/from the falc54 (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe/ ble as shown in table 1 and 2 . in table 3 is shown how the ale (address latch enable) line is used to control the bus structure and interface type. the switching of ale allows the falc54 to be directly connected to a multiplexed address/data bus.
peb 2254 general features e1 semiconductor group 25 11.96 mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. table 1 data bus access (16-bit intel mode) table 2 data bus access (16-bit motorola mode) table 3 selectable bus and microprocessor interface configuration bhe a0 register access falc54 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d8 C d15 1 0 register byte access (even addresses) d0 C d7 1 1 no transfer performed none ble a0 register access falc54 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d0 C d7 1 0 register byte access (even addresses) d8 C d15 1 1 no transfer performed none ale im microprocessor interface bus structure gnd/vdd 1 motorola demultiplexed gnd/vdd 0 intel demultiplexed switching 0 intel multiplexed
semiconductor group 26 11.96 peb 2254 general features e1 the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: siemens/intel (adr. n + 1) (adr. n) motorola (adr. n) (adr. n + 1) -- n: even address complete information concerning register functions is provided in C detailed register description. fifo structure in transmit and receive direction of the signaling controller 64-byte deep fifos are provided for the intermediate storage of data between the system internal highway and the cpu interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cpu at any time. in case 16-bit data bus width is selected by fixing pin dbw to logical 1 word access to the fifos is enabled. data output to bus lines d0-d15 as a function of the selected interface mode is shown in figure 6 and 7 . of course, byte access is also allowed.the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 2 bytes. data lines d15 d8 d7 d0
peb 2254 general features e1 semiconductor group 27 11.96 figure 6 fifo word access (intel mode)
semiconductor group 28 11.96 peb 2254 general features e1 figure 7 fifo word access (motorola mode)
peb 2254 general features e1 semiconductor group 29 11.96 interrupt interface special events in the falc54 are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; ipc register), which requests the cpu to read status information from the falc, or to transfer data from/to falc. since only one int request output is provided, the cause of an interrupt must be determined by the cpu by reading the falcs interrupt status registers (gis, isr0, isr1, isr2, isr3) that means the interrupt at pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr0-3 are from type clear on read. the structure of the interrupt status registers is shown in figure 8 . figure 8 falc54 interrupt status registers each interrupt indication of registers isr0, isr1, isr2 and isr3 can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0, imr1, imr2, imr3. if the interrupt status bits are masked they neither generate an interrupt at int nor are they visible in isr0-3. gis, the non-maskable global interrupt status register, serves as pointer to pending channel related interrupts. after the falc54 has requested an interrupt by activating its int pin, the cpu should first read the global interrupt status register gis to identify the requesting interrupt source register. after reading the assigned interrupt status registers isr0- isr3, the pointer in register gis is cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (gis is reset), pin int goes inactive. updating of interrupt status registers isr03 and gis is only prohibited during read access.
semiconductor group 30 11.96 peb 2254 general features e1 masked interrupts visible in status registers the global interrupt status register (gis) indicates those interrupt status registers with active interrupt indications (gis.isr0-3). an additional mode can be selected via bit ipc.vis. in this mode, masked interrupt status bits neither generate an interrupt at pin int nor are they visible in gis, but are displayed in the respective interrupt status register(s) isr0..3 . this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. notes: ? in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. ? all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no hierarchical polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts.
peb 2254 general functions and device architecture e1 semiconductor group 31 11.96 2 general functions and device architecture e1 2.1 functional description e1 2.1.1 receive path figure 9 receive clock system receive line interface for data input, three different data types are supported: ? ternary coded signals received at multifunction ports rl1 and rl2 from a 6 db ternary interface. the ternary interface is selected if lim1.drs is reset. ? digital dual rail signals received at ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. ? unipolar data at port roid received from a fibre optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset.
peb 2254 general functions and device architecture e1 semiconductor group 32 11.96 receive clock and data recovery the analog received signal at port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal at port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rclk from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single rail, unipolar bit stream. the clock and data recovery works with the frequency supplied by xtal1 and xtal2. normally the clock that is output via pin rclk is the recovered clock from the signal provided by rl1/2 or rdip/n has a duty cycle close to 50 %. the free run frequency is defined by xtal1/2 devided by 8 in periods with no signal. receive line coding the hdb3 line code or the ami coding is provided for the data received from the ternary or the dual rail interface. in case of the optical interface a selection between the nrz code and the cmi code (1t2b) with hdb3 postprocessing is provided. if cmi code (1t2b) is selected the receive route clock will be recovered from the data stream. the 1t2b decoder does not correct any errors. in case of nrz coding data will be latched with the falling edge of pin rclki. the hdb3 code is used along with double violation detection or extended code violation detection (selectable). in ami code all code violations will be detected. the detected errors increment the code violation counter (16 bits length). when using the optical interface with nrz coding, the decoder is by-passed and no code violations will be detected. additionally, the receive line interface comprises the alarm detection for alarm indication signal ais, the loss of signal los and the auxiliary pattern auxp (unframed and continuous bitstream of alternating ones and zeros). the signal at the ternary interface is received at both ends of a transformer. the operating modes 75 or 120 w are selectable by switching resistors in parallel. this selection does not require changing transformers. figure 10 receiver configuration
peb 2254 general functions and device architecture e1 semiconductor group 33 11.96 recommended receiver configuration values jitter free system clocks (16 / 8 / 4 / 2 mhz and 8 khz) are generated by the internal pll circuit dco1. the dco1 can work in two different modes: ? slave mode in slave mode, the dco1 will be synchronized on the recovered route clock. in case of los the dco1 switches automatically to master mode. ? master mode in master mode the oscillator is in free running mode if pin sync is connected to vss. if there is a frequency of 2.048 mhz at the sync input the dco1 is then synchronized to this input. loss of signal detection there are different definitions for detecting loss of signal (los) alarms in the itu-t g.775 and ets 300233. the falc54 covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register ipc.sci. ? detection: an alarm will be generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. no pulse in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for no pulse in the analog receive interface (lim1.drs=0). the receive signal level q is programmable via three control bits lim1.ril2-0 in a range of about 1400 to 200 mv differential voltage between pins rl1/2. the number n can be set via an 8 bit register pcd. the contents of the pcd register will be multiplied by 16, which results in the number of pulse periods or better, the time which has to suspend until the alarm has to be detected. the range results therefore from 16 to 4096 pulse periods. ets300233 requires detection intervals of at least 1 ms. this time period results always in a lfa (loss of frame alignment) before a los will be detected. ? recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2-0) of the nominal pulse. the value in the 8 bit register pcr parameter characteristic impedance [ w ] 120 75 r 1 ( 2.5 %) [ w ]250 t 2 : t 1 1 : ? 21 : ? 2 r 2 ( 2.5 %) [ w ] 190 150
peb 2254 general functions and device architecture e1 semiconductor group 34 11.96 defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. jitter attenuator together with a pll and a tunable crystal attenuation of received input jitter is done in the clock- and data-recovery and either in the received elastic buffer (2 frames) or in the jitter attenuator jatt block of figure 3. the attenuator consists of a 288 bit fifo. the fifo is placed in the transmitter and will be active if bit lim1.jatt=1 , remote loop or xslicer mode active. the jitter attenuator meets the jitter transfer requirements of the rec. i.431 and g.735/736 (refer to figure 11 ). figure 11 jitter attenuation performance also the requirements of etsi tbr12/13 will be satisfied. insuring adequate margin against tbr12/13 output jitter limit with 15 ui input at 20 hz the falc54 will start jitter attenuation at nearly 2 hz.
peb 2254 general functions and device architecture e1 semiconductor group 35 11.96 jitter tolerance the falc54 receivers tolerance to input jitter complies to itu for cept application. figure 12 shows the curves of different input jitter specifications stated above as well as the falc54 performance. figure 12 jitter tolerance output jitter in the absence of any input jitter the falc54 generates the output jitter, which is specified in table below. specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff i.431 20 hz 100 khz < 0.015 700 hz 100 khz < 0.015
peb 2254 general functions and device architecture e1 semiconductor group 36 11.96 clock generation and clock modes the high performance integrated clock generator meets the recommendations of itu-t g.735, g824 and i.431 in case of input jitter tolerance, jitter transfer characteristic and output jitter. the following table shows the clock modes with the corresponding synchronization sources. the clock generator unit fulfills two main tasks. one is, to provide jitter free system clocks either derived from the line or from an external input. the other task is either smoothing the sclkx input in atm, sonet or sdh applications (xslicer mode) or to ensure output jitter characteristics in case jittered sclkx clock. the system clocks are provided by the dco1 (16 m, 8 m, 4/2 m, 8 k). the recovered route clock is directly forwarded to the pll circuit (in slave mode). the main task of dco2 is to generate a jitter free transmit clock if the xslicer function is enabled. in this case a 16.384 mhz crystal has to be connected to pins xtal3/4. mode internal los active sync input system clocks master no gnd free running (oscillator centered) master no 2 mhz synchronized on sync input (external 2 mhz) slave no gnd synchronized on line (rclk) slave no 2 mhz synchronized on line (rclk) slave yes gnd free running (oscillator centered) slave yes 2 mhz synchronized on sync input (external 2 mhz)
peb 2254 general functions and device architecture e1 semiconductor group 37 11.96 figure 13 transmit clock system framer/synchronizer the following functions are performed: ? synchronization on pulse frame ? synchronization on multiframe ? error indication when synchronization is lost. in this case, ais is automatically sent to the system side and remote alarm to the remote end if en/disabled. ? initiating and controlling of resynchronization after reaching the asynchronous state. this may be automatically done by the falc54, or user controlled via the microprocessor interface. ? detection of remote alarm indication from the incoming data stream. ? separation of service bits and data link bits. this information is stored in special status registers. ? generation of various interrupt statuses of the receiver functions. these interrupts can be masked. ? generation of control signals to synchronize the crc checker, and the receive elastic store write control unit.
peb 2254 general functions and device architecture e1 semiconductor group 38 11.96 if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc submultiframe according to the crc 4 procedure ( refer to itu-t rec. g704 ). these bits are compared with those check bits that are received during the next crc submultiframe. if there is at least one mismatch, the crc error counter (16 bit) will be incremented. receive elastic store the received bit stream is stored in the receive elastic store. the memory is organized as a two-frame elastic buffer with a size of 64 8 bit. the functions are: ? clock adaption between system clock (sclkr) and internally generated route clock (rclk). ? compensation of input wander and jitter. maximum of wander amplitude (peak-to-peak): 190 ui (1 ui = 488 ns) ? frame alignment between system frame and receive route frame ? reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, channel-serial data which is circularly written to the elastic store using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock (sclkr) and the synchronous pulse ( sypr) in conjunction with the programmed offset values for the receive time-slot/clock-slot counters. after conversion into a serial data stream, the data is given out via port rdo. two bit rates (2048/4096 kbit/s) are selectable via the microprocessor interface. in 4096 kbit/s interface mode each channel will be sent out on two different channel- phases. each channel-phase which should be tri-stated is programmable. figure 14 gives an idea of operation of the receive elastic store: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the write pointer is within the slip limits (s +, s C). if a slip condition is detected, a negative slip (the next received frame is skipped) or a positive slip (the previous received frame is read out twice) is performed at the system interface, depending on the difference between rclk and sclkr/4, i.e. on the position of pointer r and w within the memory.
peb 2254 general functions and device architecture e1 semiconductor group 39 11.96 figure 14 the receive elastic store as circularly organized memory additionally the receive elastic store can be switched to one frame length (loop.sfm). this feature is useful for master-slave applications to reduce the delay between line interface and system interface. for correct operation, system clock sclkr has to be connected to pin clk8m and synchronous pulse sypr has to be connected to the pin fsc of the falc54. in single frame mode, however, it is not possible to perform a slip after the slip condition has been detected. thus, values of receive time-slot/clock-slot offset (rc0, rc1) have to be specified great enough to prevent too great approach of frame begin (line side) and frame begin (system side).
peb 2254 general functions and device architecture e1 semiconductor group 40 11.96 receive signaling controller the receive signaling controller can be programmed to operate in various signaling modes. the falc54 will perform the following signaling and data link methods: ? message oriented signaling also called common channel signaling ccs ? channel associated signaling cas the signaling information is carried in time-slot 16 (ts16). the signaling controller samples the bit stream which is output on pin rdo. in case of channel associated signaling data is sampled on the receive line side clocked with the extracted receive route clock and stored in registers rs1-16. the signaling procedure will be done as it is described in itu-t g.704 and g.732. the main functions are: ? synchronization to a cas multiframe ? detection of ais and remote alarm in cas multiframes ? separation of cas service bits x1-x3 ? storing of received signaling data in registers rs1-16. updating of the received signaling information is inhibited if the ts0 or ts16 multiframe alignment is lost. in case of common channel signaling the signaling procedure hdlc/sdlc will be supported. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the falc54 can perform a 1 or 2 byte address recognition. all frames with valid addresses are forwarded directly via the receive fifo (rfifo) to the system memory. the hdlc control-field, data in the i-field and an additional status byte are temporarily stored in the rfifo. the hdlc control-field and additional information can also be read from special registers. in extended transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows the user specific protocol variations. the received data are stored in the rfifo. the falc54 offers the flexibility to extract data during certain time-slots which are defined via registers rtr1-4 or to extract the s a bits enabled via xc0.sa8e-4e. any combination of time-slots or s a bits can be programmed. 2.1.2 transmit path the inverse functions are performed for the transmit direction. the pcm data is received from the system internal highway at port xdi with 2048 kbit/s or 4096 kbit/s. the channel assignment is equivalent to the receive direction. the contents of selectable channels (time-slots) can be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the four-byte registers icb1 icb4.
peb 2254 general functions and device architecture e1 semiconductor group 41 11.96 latching of data is controlled by the system clock (sclkx) and the synchronous pulse ( sypx) in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters. the clock for the transmit data is internal derived directly from the system clock (sclkx). consequently, the data received from the system interface is switched through. transmit signaling controller similar to the receive signaling controller the same signaling methods and the same time-slot assignment are provided. the signaling information has to be written in the transmit fifo (xfifo). with a transmit frame command the signaling information will be sent in the corresponding time-slots. the signaling will be internally multiplexed with the data at port xdi. if the extended transparent mode is selected, the falc54 supports the continuous transmission of the contents of the xfifo. the cyclic transmission continuous until the transmitter reset command (cmdr.sres) is issued or cmdr.xrep is reset. in case of channel associated signaling the complete cas multiframe have to be written to the xs1-16 registers. the contents of these registers will be sent in ts16. in case of ccs the signaling procedure hdlc/sdlc is supported with generation of preambles and flags, crc generation and bit-stuffing. in transmit direction the falc54 offers the flexibility to insert data during certain time-slots which are defined via registers ttr1-4 or to insert the s a bits enabled via xc0.sa8e-4e. any combination of time-slots bits can be programmed independent for the receive and transmit direction. if the falc54 is optioned for no signaling, the channels in the data stream from the system interface will pass the falc54 undisturbed. transmitter the serial bit stream is then processed by the transmitter which has the following functions: ? frame/multiframe synthesis of one of the two selectable framing formats ? insertion of service and data link information ? ais generation (alarm indication signal) ? remote alarm generation ? auxiliary pattern generation ? crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error the multiframe boundries of the transmitter may be externally synchronized by using the xmfs pin. this feature is required if signaling- and service- bits are routed through the switching network and are inserted in transmit direction via the system interface.
peb 2254 general functions and device architecture e1 semiconductor group 42 11.96 transmit line interface the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by the digital transmitter. figure 15 transmitter configuration recommended transmitter configuration values similar to the receive line interface three different data types are supported: ? ternary signal single rail data is converted into a ternary signal which is output on pins xl1 and xl2. the hdb3 and ami line code is employed. selected by fmr0.xc1/0 and lim1.drs = 0. ? dual rail data pcm(+), pcm(C) at multifunction ports xdop/ xdon with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0.xc1/0 and lim1.drs = 1. ? unipolar data at port xoid will be transmitted either in nrz (non return to zero) with 100 % duty cycle or in cmi (code mark inversion or known as 1t2b) code with or without (fmr3.cmi) preprocessed hdb3 coding to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock xclk (2048 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. the analog transmitter includes a programmable pulse shaper to satisfy the requirements of itu-t i.431. the amplitude of pulse shaper is programmable via the microprocessor interface to allow a maximum of different pulse templates. the transmitter requires an external step up transformer to drive the line. parameter characteristic impedance [ w ] 120 75 r 1 ( 2.5 %) [ w ]1818 t 2 : t 1 1 : ? 21 : ? 2
peb 2254 general functions and device architecture e1 semiconductor group 43 11.96 transmit line monitor the transmit line monitor compares the transmit line pulses on xl1 and xl2 with the transmit input signals received on pins xl1m and xl2m. the monitor detects faults on the primary side of the transformer and protects the device from damage by setting the transmit line driver xl1/2 automatically in a high impedance state. faults on the secondary side may not be detected. to detect a short the configuration in figure 15 and the reset values of register xpm0-2 has to be fulfilled. otherwise the short detection could not be guaranteed. two conditions will be detected by the monitor: transmit line ones density (more than 31 consecutive zeroes) and transmit line shorted. in both cases a transmit line monitor status change interrupt will be provided. figure 16 transmit line monitor configuration 2.1.3 additional functions idle code insertion in transmit direction, the contents of selectable channels can be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the four-byte registers icb1 icb4. transparent mode the described transparent modes are useful for loopbacks or for routing signaling information through the system interface. in receive direction, transparency for ternary or dual / single rail unipolar data is always achieved if the receiver is in the synchronous state. in asynchronous state the data can be transparently switched through if bit fmr2.dais and bit fmr2.rtm are set. however, correct time-slot assignment can not be guaranteed due missing frame alignment between line and system side.
peb 2254 general functions and device architecture e1 semiconductor group 44 11.96 transparency in transmit direction can be achieved by activating the time-slot 0 transparent mode (bit xsp.tt0 or tswm.7-0). if xsp.tt0 = 1 all internal information of the falc54 (framing, crc, sa/si bit signaling, remote alarm) will be ignored. with register tswm the si-bits, a-bit or the sa4-8 bits could be selectively enabled to send data transparent from port xdi to the far end. only hdb3 data encoding is still provided. for complete transparency the internal signaling controller and payload loop back has to be disabled. system clocks and system pulses for transmitter and receiver the falc54 offers a flexible feature for system designers where different system clocks and system pulses are necessary. the interface to the receive system highway will be clocked via pin sclkr, while the interface to the transmit system highway is clocked via pin sclkx. the frequency on pin sclkr/x must fixed 8.192 mhz. the signals on pin sypr in conjunction with the assigned timeslot offset in register rc0 and rc1 will define the beginning of a frame on the receive system highway.the signal on pin sypx in conjunction with the assigned timeslot offset in register xc0 and xc1 will define the beginning of a frame on the transmit system highway. error performance monitoring the falc54 supports the error performance monitoring by detecting following alarms in the received data. ? framing errors ? crc errors ? code violations ? loss of frame alignment ? loss of signal ? alarm indication signal ? e bit error ? slip with a programmable interrupt mask (register imr4) all these error events could generate an errored second interrupt (es) if enabled. additionally a one second interrupt could be generated to indicate that the es interrupt has to be read. if the es interrupt is set the enabled alarm status bits or the error counters have to be examined. automatic remote alarm access if the receiver has lost its synchronization a remote alarm could be sent if enabled via bit fmr2.axra to the distant end. the remote alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be removed.
peb 2254 general functions and device architecture e1 semiconductor group 45 11.96 2.1.4 operating modes e1 general bit: fmr1.pmod = 0 pcm line bit rate : 2048 kbit/s single frame length : 256 bit, no .1256 framing frequency : 8 khz hdlc controller : organization : 32 time-slots, no. 0 31 with 8 bits each, no. 1 8 the operating mode of the falc54 is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc54 implements all of the standard and/or common framing structures for pcm 30 (cept, 2048 kbit/s) carriers. these are summarized in table 4 , along with the signaling types applicable in each of the multiframe formats. general signaling refers to the support the falc54 provides for handling the service bits, as the case may be, in the multiframe. table 4 summary of falc54 framing and supported signaling modes ccs = common channel signaling cas-cc = channel associated signaling (common channel) for ccs and cas-cc, different types of support are provided. note: the internal hdlc- or cas controller supports all signaling procedures like signaling frame synchronization / synthesis and signaling alarm detection. double-frame crc-multi-frame crc C crc4 signaling ccs cas-cc cas-br e.g. ts16 e.g. ts16 C e.g. ts16 e.g. ts16 C general signaling s bits s bits
peb 2254 general functions and device architecture e1 semiconductor group 46 11.96 the next pages give a general description of the assigned framing formats. after reset, the falc54 is switched into doubleframe format automatically. time-slot 0 is reserved for frame alignment word and service information. switching between the two applicable framing formats (doubleframe/crc-multiframe) is done via bit fmr2.rfs1/0 for the receiver and fmr1.xfs for the transmitter. line interfacing ? dual rail data with ami or hdb3 coding in conjunction with double violation detection or extended code violation detection (fmr0.extd). errors can be counted by the code violation counter cvc with 16 bit length. ? single rail unipolar data (fmr0.xc1/0) with nrz or cmi code. ? general alarms ? ais: detection is flagged by bit frs0.ais. transmission is enabled via bit fmr1.xais. ? los: detection is flagged by bit frs0.los. ? rai: remote alarm indication is flagged by bit frs0.rra and rsw.rra. transmission is enabled via bit xsw.xra. ? auxp: detection is flagged by bit frs1.auxp. transmission is enabled via bit xsp.xap. channel assignment the channel (time-slot) assignment from the pcm line to the system internal highway is performed without any changes of channel numbering (ts0 ? ts0, , ts31 ? ts31). in receive direction, the contents of time-slot 0 are switched through transparently. in transmit direction, contents of time-slot 0 of the outgoing pcm frame are normally generated by the falc54. additionally, one transparent mode (xsp.tt0) can be selected to achieve transparency for the complete time-slot 0. with the transparent service word mask register (tswm) the si-bits, a-bit and the sa4-8 bits could be selectively switched through transparently. general signaling ?s a bits in accordance with itu-t g.704 and ets 300233. ? e bits in accordance with itu-t g.704 and ets 300233.
peb 2254 general functions and device architecture e1 semiconductor group 47 11.96 signaling ? ccs for common channel signaling the use of time-slot 16 is recommended. the use of ccs is allowed with both the doubleframe and the crc-multiframe format. ? cas-cc for channel associated signaling the use of time-slot 16 is recommended. the autonomous cas multiframe structure is not related to a doubleframe or a crc-multiframe structure (refer to itu-t g.704 ). the falc54 support cas multiframe synchronization and synthesis. 2.1.4.1 doubleframe format the framing structure is defined by the contents of time-slot 0 (refer to table 5 ). table 5 allocation of bits 1 to 8 of time-slot 0 note: 1. s i bits: reserved for international use. if not used, these bits should be fixed to 1. access to received information via bits rsw.rsi and rsp.rsif. transmission is enabled via bits xsw.xsis and xsp.xsif. 2. fixed to 1. used for synchronization. 3. remote alarm indication: in undisturbed operation 0; in alarm condition 1. 4. s a bits: reserved for national use. if not used, they should be fixed at 1. access to received information via bits rsw.ry0 ry4. transmission is enabled via bits xsw.xy0 xy4. hdlc-signaling in bits sa4- sa8 is selectable. (*) note: (*) as a special extension for double frame format, the s a -bit registers rsa4-8 / xsa4-8 may be used optionally. bit alternate number frames 12 345678 frame containing the frame alignment signal s i 0 011011 note 1 frame alignment signal frame not containing the frame alignment signal s i 1as a4 s a5 s a6 s a7 s a8 note 1 note 2 note 3 note 4
peb 2254 general functions and device architecture e1 semiconductor group 48 11.96 for transmit direction, contents of time-slot 0 are additionally determined by the selected transparent mode: 1) additionally, automatic transmission of the a-bit is selectable 2) as a special extension for double frame format, the sa-bit register may be used optionally . synchronization procedure synchronization status is reported via bit frs0.lfa. framing errors are counted by the framing error counter (fec). asynchronous state is reached after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time-slot 0 of every other frame not containing the frame alignment word), the selection is done via bit rc1.asy4. additionally, the service word condition can be disabled. when the framer lost its synchronization an interrupt status bit isr2.lfa is generated. in asynchronous state, counting of framing errors will be stopped and ais is automatically sent to the system internal highway (can be disabled via bit fmr2.dais). the resynchronization procedure starts automatically after reaching the asynchronous state. additionally, it may be invoked user controlled via bit: fmr0.frs (force resynchronization: the fas word detection is interrupted. in connection with the above conditions this will lead to asynchronous state. after that, resynchronization starts automatically). synchronous state is established after detecting: C a correct fas word in frame n, C the presence of the correct service word (bit 2 = 1) in frame n + 1, C a correct fas word in frame n + 2. if the service word in frame n + 1 or the fas word in frame n + 2 or both are not found searching for the next fas word will be start in frame n + 2 just after the previous frame alignment signal. reaching the synchronous state causes a frame alignment recovery interrupt status isr2.far if enabled. undisturbed operation starts with the beginning of the next doubleframe. transparent source for mode framing a bit s a bits s i bits C xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa4-8 (int. generated) via pin xdi (int. generated) (int. generated) (int. generated) (int. generated) xsw.xra 1) via pin xdi xsw.xra xsw.xra via pin xdi xsw.xra xsw.xy0 4 2) via pin xdi xsw.xy0 4 xsw.xy0 4 xsw.xy0 4 via pin xdi xsw.xsis, xsp.xsif via pin xdi via pin xdi via pin xdi xsw.xsis, xsp.xsif xsw.xsis, xsp.xsif
peb 2254 general functions and device architecture e1 semiconductor group 49 11.96 a-bit access if the falc54 detects a remote alarm indication in the received data stream the interrupt status bit isr2.ra will be set. by setting fmr2.axra the falc54 automatically transmit the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment frs0.lfa = 1. if the receiver is in synchronous state frs0.lfa = 0 the remote alarm bit will be reset. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table 6 ). s a - bit access as an extension for access to the s a -bits via registers rsa4-8/xsa4-8 an option is implemented to allow the usage of internal s a -bit registers rsa4-8/xsa4-8 in doubleframe format. this function is enabled by setting fmr1.ensa = 1 for the transmitter and fmr1.rfs1/0 = 01 for the receiver. the falc54 works then internally with a 16-frame structure but no crc multiframe alignment/generation is performed. for more details refer to chapter 2.1.4.2 . 2.1.4.2 crc-multiframe the multiframe structure shown in table 6 is enabled by setting bit: fmr1.rfs1 for the receiver and fmr1.xfs for the transmitter. multiframe : 2 submultiframes = 2 8 frames frame alignment : refer to section doubleframe format multiframe alignment : bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern 001011 crc bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14 crc block size : 2048 bit (length of a submultiframe) crc procedure : crc4, according to itu-t rec. g.704, g.706
peb 2254 general functions and device architecture e1 semiconductor group 50 11.96 table 6 crc-multiframe structure e: spare bits for international use. access to received information via bits rsp.rs13 and rsp.rs15. transmission is enabled via bits xsp.xs13 and xsp.xs15. additionally, automatic transmission for submultiframe error indication is selectable. s a : spare bits for national use. additionally, sa bit access via registers rsa4 8 and xsa4 8 is provided. hdlc-signaling in bits sa4- sa8 is selectable. c 1 c 4 : cyclic redundancy check bits. a: remote alarm indication. additionally, automatic transmission of the a-bit is selectable. sub- multiframe frame number bits 1 to 8 of the frame 123456 78 multiframe i 0 1 2 3 4 5 6 7 c 1 0 c 2 0 c 3 1 c 4 0 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8 ii 8 9 10 11 12 13 14 15 c 1 1 c 2 1 c 3 e* c 4 e* 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8
peb 2254 general functions and device architecture e1 semiconductor group 51 11.96 for transmit direction, contents of time-slot 0 are additionally determined by the selected transparent mode: 1) automatic transmission of the a-bit is selectable 2) the s a -bit register xsa4-8 may be used optionally 3) additionally, automatic transmission of submultiframe error indication is selectable the crc procedure is automatically invoked when the multiframe structure is enabled. crc errors in the received data stream are counted by the 16 bit crc error counter cec (one error per submultiframe, maximum). additionally a crc4 error interrupt status isr0.crc4 can be generated if enabled via imr0.crc4. all crc bits of one outgoing submultiframe are automatically inverted in case a crc error is flagged for the previous received submultiframe. this function is enabled via bit rc0.crci. setting the bit rc0.xcrci will invert the crc bits before transmission to the distant end. the function of rc0.xcrci and rc0.crci are logically ored. synchronization procedure multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged at status bits frs0.lfa and frs0.lmfa). the rising edge of these bits will cause an interrupt status bits isr2.lfa + isr2.lmfa. the multiframe resynchronization procedure starts when doubleframe alignment has been regained which is indicated by an interrupt status bit isr2.far. for doubleframe synchronization refer to section doubleframe format. it may also be invoked by the user by setting C bit fmr0.frs for complete doubleframe and multiframe re-synchronization C bit fmr1.mfcs for multiframe re-synchronization only. the crc checking mechanism will be enabled after the first correct multiframe pattern has been found. however, crc errors will not be counted in asynchronous state. transparent source for mode framing + crc a bit sa bits e bits C xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa4C8 (int. generated) via pin xdi (int. generated) (int. generated) (int. generated) (int. generated) xsw.xra 1) via pin xdi xsw.xra 1) xsw.xra 1) via pin xdi xsw.xra 1) xsw.xy0 4 2) via pin xdi xsw.xy0 4 2) xsw.xy0 4 2) xsw.xy0 4 2) via pin xdi xsp.xs13/xs15 3) via pin xdi (int. generated) via pin xdi xsp.xs13/xs15 3) xsp.xs13/xs15 3)
peb 2254 general functions and device architecture e1 semiconductor group 52 11.96 the multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n 2 ms (n = 1, 2, 3 ). the loss of multiframe alignment flag frs0.lmfa will be reset. additionally an interrupt status multiframe alignment recovery bit isr2.mfar is generated with the falling edge of bit frs0.lmfa. automatic force resynchronization in addition, a search for doubleframe alignment is automatically initiated if two multiframe pattern with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained (bit fmr1.afr). the research for frame alignment will be started just after the previous frame alignment signal. floating multiframe alignment window after reaching doubleframe synchronization a 8 ms timer is started. if a multiframe alignment signal is found during the 8 ms time interval the internal timer will be reset to remaining 6 ms in order to find the next multiframe signal within this time. if the multiframe signal is not found for a second time an interrupt status isr0. t8ms will be provided. this interrupt will usually occur every 8 ms until multiframe synchronization is achieved. crc4 performance monitoring in the synchronous state checking of multiframe pattern is disabled. however, with bit fmr2.almf an automatic multiframe resynchronization mode can be activated. if 915 out of 1000 errored crc submultiframes are found then a false frame alignment will be assumed and a search for double- and multiframe pattern is initiated. the new search for frame alignment will be started just after the previous basic frame alignment signal. the internal crc4 resynchronization counter will be reset when the multiframe synchronization has been regained. modified crc4 multiframe alignment algorithm the modified crc4 multiframe alignment algorithm allows an automatic interworking between framers with and without a crc4 capability. the interworking is realized as it is described in itu-t g.706 appendix b. if doubleframe synchronization is consistently present but crc4 multiframe alignment is not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe format. the crc4 - non crc4 interworking is enabled via fmr2.rfs1/0 = 11 and is activated only if the receiver has lost its synchronization. if doubleframe alignment (basic frame alignment) is established a 400 ms timer and searching for multiframe alignment will be started. a research for basic frame alignment will be initiated if the crc4 multiframe synchronization could not be achieved within 8 ms and will be started just after the previous frame alignment signal. the research of the basic frame alignment is done in parallel and is independent of the synchronization procedure of the primary basic
peb 2254 general functions and device architecture e1 semiconductor group 53 11.96 frame alignment signal. during the parallel search all receiver functions are based on the primary frame alignment signal, like framing errors, sa-, si-, a-bits ). all subsequent multiframe searches are associated with each basic framing sequence found during the parallel search. if the crc4 multiframe alignment sequence was not found within the time interval of 400 ms, the receiver will be switched into a non crc4 mode indicated by setting the bit frs0.nmf (no multiframing found) and isr2.t400ms. in this mode checking of crc bits is disabled and the received e-bits are forced to low. the transmitter framing format will not be changed. even if multiple basic fas resynchronizations have been established during the parallel search, the receiver will be maintained to the initially determined primary frame alignment signal location. however, if the crc4 multiframe alignment could be achieved within the 400 ms time interval assuming a crc4 to crc4 interworking, then the basic frame alignment sequence associated to the crc4 multiframe alignment signal will be chosen. if necessary, the primary frame alignment signal location will be adjusted according to the multiframe alignment signal. the crc4 performance monitoring will be started if enabled via fmr2.almf and the received e-bits will be processed in accordance with itu-t g.704. switching into the doubleframe format (non crc4) mode after 400 msec can be disabled by setting of fmr3.extiw. in this mode the falc54 still searches the multiframing further on. a-bit access if the falc54 detects a remote alarm indication (bit 2 in ts0 not containing the fas word) in the received data stream the interrupt status bit isr2.ra will be set. with the deactivation of the remote alarm the interrupt status bit isr2.rar is generated. by setting fmr2.axra the falc54 automatically transmits the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment (frs0.lfa = 1). if the receiver is in synchronous state (frs0.lfa = 0) the remote alarm bit will be reset in the outgoing data stream. additionally, if bit fmr3.extiw is set and the multiframesynchronous state could not be achieved within the 400 msec after finding the primary basic framing, the a-bit will be transmitted active high to the remote end until the multiframing is found. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table 6 ).
peb 2254 general functions and device architecture e1 semiconductor group 54 11.96 s a - bit access due to signaling procedures using the five s a bits (s a4 s a8 ) of every other frame of the crc multiframe structure, three possibilities of access via the microprocessor are implemented. ? the standard procedure allows reading/writing the s a -bit registers rsw, xsw without further support. the s a -bit information will be updated every other frame. ? the advanced procedure, enabled via bit fmr1.ensa, allows reading/writing the s a -bit registers rsa4 8, xsa4 8. a transmit or receive multiframe begin interrupt (isr0.rmb or isr1.xmb) is provided. registers rsa4-8 contains the service word information of the previously received crc-multiframe or 8 doubleframes (bitslots 4-8 of every service word). these registers will be updated with every multiframe begin interrupt isr0.rmb. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of this registers xsa4-8 will be copied into shadow registers. the contents will subsequently sent out in the service words of the next outgoing crc multiframe (or doubleframes) if none of the time-slot 0 transparent modes is enabled. the transmit multiframe begin interrupt xmb request that these registers should be serviced. if requests for new information will be ignored, current contents will be repeated. ? the extended access via the receive and transmit fifos of the signaling controller. in this mode it is possible to transmit / receive a hdlc frame or a transparent bit stream in any combination of the s a bits. enabling is done by setting of bit ccr1.eits and the corresponding bits xc0.sa8e-4e / tswm.tsa8-4 and resetting of registers ttr1-4, rtr1-4 and fmr1.ensa. the access to and from the fifos is supported by isr0.rme,rpf and isr1.xpr,als.
peb 2254 general functions and device architecture e1 semiconductor group 55 11.96 sa6-bit detection according to ets 300233 four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the falc54 will detect following fixed sa6-bit combinations: sa61,sa62,sa63,sa64 = 1000; 1010; 1100; 1110; 1111. all other possible 4 bit combinations are grouped to status x. a valid sa6-bit combination must occur three times in a row. the corresponding status bit in register rsa6s will be set. register rsa6s is from type clear on read. with any change of state of the sa6-bit combinations an interrupt status isr0.sa6sc will be generated. during the basicframe asynchronous state updating of register rsa6s and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synch. state (frs0.lmfa=0). in asynchr. detection mode updating is independent to the multiframe synchronous state. sa6 bit error indication counters the sa6 bit error indication counter crc2l/h (16 bits) counts the received sa6 bit sequence 0001 or 0011 in every crc submultiframe.in the primary rate access digital section this counter option gives information about crc errors reported from the te via sa6 bit. incrementing is only possible in the multiframe synchronous state. the sa6 bit error indication counter crc3l/h (16 bits) counts the received sa6 bit sequence 0010 or 0011 in every crc submultiframe. in the primary rate access digital section this counter option gives information about crc errors detected at t-reference point and reporting them via the sa6 bit. incrementing is only possible in the multiframe synchronous state.
peb 2254 general functions and device architecture e1 semiconductor group 56 11.96 e-bit access due to signaling requirements, the e bits of frame 13 and frame 15 of the crc multiframe can be used to indicate received errored submultiframes: submultiframe i status e- bit located in frame 13 submultiframe ii status e- bit located in frame 15 no crc error: : e = 1 crc error: : e = 0 standard procedure after reading the submultiframe error indication rsp.si1 and rsp.si2, the microprocessor has to update contents of register xsp (xs13, xs15). access to these registers has to be synchronized to transmit or receive multiframe begin interrupts (isr0.rmb or isr1.xmb). in the double- and multiframe asynchronous state the e-bits are set to zero. however they can be set to one in the async. state if enabled via bit xsp.ebp. in the multiframe sync. state the e-bits are processed according to itu-t g.704 independent of bit xsp.ebp. automatic mode by setting bit xsp.axs status information of received submultiframes is automatically inserted in e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. submultiframe error indication counter the ebc (e-bit) counter ebcl and ebch (16 bits) counts zeros in e-bit position of frame 13 and 15 of every received crc multiframe. this counter option gives information about the outgoing transmit pcm line if the e bits are used by the remote end for submultiframe error indication. incrementing is only possible in the multiframe synchronous state. note: e-bits may be processed via the system interface. setting bit tswm.tsis enables transparency for e bits in transmit direction (refer to table 6 ).
peb 2254 general functions and device architecture e1 semiconductor group 57 11.96 2.1.4.3 test functions there are two types of monitoring/testing functions: ? active tests which partly degrade the functionality (e.g. payload loop, remote loop, local loop, test loop for a single channel). ? diagnostics, during which the device is not operational (e.g. diagnostic loop of an entire trunk). single channel loop back each of the 32 channels may be selected for loopback from the system pcm input (xdi) to the system pcm output (rdo). this loopback is programmed for one channel at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route channel. for the channel test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested channel will disturb testing. these slips do not influence the other channels and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 17 single channel loopback
peb 2254 general functions and device architecture e1 semiconductor group 58 11.96 payload loop back to perform an effective circuit test a payload loop is implemented. the payload loop back (fmr2.plb) will loop the data stream from the receiver section back to transmitter section. the looped data will pass the complete receiver including the wander and jitter compensation in the receive elastic store and were output on pin rdo. instead of the data an ais (fmr2.sais) could be sent to the system interface. the framing bits, crc4 and spare bits are not looped. they are originated by the falc54 transmitter. when the plb is enabled the transmitter and the data on pins xl1/2 or xdop/xdon are clocked with sclkr instead of sclkx. data on pin xdi are ignored. all the received data are processed normally. figure 18 payload loop
peb 2254 general functions and device architecture e1 semiconductor group 59 11.96 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream will be undisturbed transmitted on the line. however an ais to the distant end could be enabled by setting fmr1.xais without influencing the data looped back to the system interface. note that enabling the local loop will usually invoke an out of frame error until the receiver can resync to the new framing. the serial code from the transmitter and receiver has to be programmed identically. figure 19 local loop
peb 2254 general functions and device architecture e1 semiconductor group 60 11.96 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl+jatt. received data may be looped with or without the transmit jitter attenuator (fifo). figure 20 remote loop
peb 2254 general functions and device architecture e1 semiconductor group 61 11.96 alarm simulation alarm simulation does not affect the normal operation of the device, i.e. all channels remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: ? loss of signal ? alarm indication signal (ais) ? auxiliary pattern ? loss of pulse frame ? remote alarm indication ? receive slip indication ? framing error counter ? code violation counter (hdb3 code) ? crc4 error counter ? e-bit error counter ? cec2 counter ? cec3 counter some of the above indications are only simulated if the falc54 is configured in a mode where the alarm is applicable (e.g. no crc4 error simulation when doubleframe format is enabled). C setting of the bit fmr0.sim initiates alarm simulation, interrupt status bits will be set. error counting and indication will occurs while this bit is set. after it is reset all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. alarms like ais and los are cleared automatically. interrupt status register and error counters are automatically cleared on read.
peb 2254 general functions and device architecture e1 semiconductor group 62 11.96 2.2 signaling controller operating modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode register. 2.2.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the falc54 can perform a 1 or 2 byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the falc54 can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc. in case of a 1-byte address, ral1 and ral2 will be used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from register rsis. as defined by the hdlc protocol, the falc54 perform the zero bit insertion/deletion (bit-stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least after 5 consecutive 1-s a 0 will appear. non-auto mode (mode.mds2-1=01) characteristics: address recognition, flag - and crc generation/check, bit-stuffing all frames with valid addresses are forwarded directly via the rfifo to the system memory.
peb 2254 general functions and device architecture e1 semiconductor group 63 11.96 transparent mode 1 (mode.mds2-0=101) characteristics: address recognition, flag - and crc generation/check, bit-stuffing only the high byte of a 2-byte address field will be compared with registers rah1/2. the whole frame excluding the first address byte will be stored in rfifo. transparent mode 0 (mode.mds2-0=100) characteristics: flag - and crc generation/check, bit-stuffing no address recognition is performed and each frame will be stored in the rfifo. 2.2.2 extended transparent mode characteristics: fully transparent in extended transparent mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit-stuffing. this feature can be profitably used e.g for: ? specific protocol variations ? test purposes data transmission is always performed out of the xfifo. in transparent mode, the receive data are shifted into the rfifo.
peb 2254 general functions and device architecture e1 semiconductor group 64 11.96 receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 23 receive data flow of falc
peb 2254 general functions and device architecture e1 semiconductor group 65 11.96 transmit data flow the frames can be transmitted as shown below. figure 24 transmit data flow of falc54 transmitting a hdlc frame via register cmdr.xtf, the address, the control fields and the data field have to be entered in the xfifo.
peb 2254 general functions and device architecture e1 semiconductor group 66 11.96 2.2.3 special functions shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. preamble transmission if enabled via register ccr3, a programmable 8-bit pattern (register pre) is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent out. zero bit insertion is disabled during preamble transmission. to guarantee correct function the programmed preamble value should be different from receive address byte values. transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds2-0 = 111), the falc54 performs fully transparent data transmission and reception without hdlc framing, i.e. without ? flag insertion and deletion ? crc generation and checking ? bit-stuffing in order to enable fully transparent data transfer, bit mode.hrac has to be set and ff h has to be written to rah2. data transmission is always performed out of xfifo by directly shifting the contents of xfifo in the outgoing datastream. transmission is initiated by setting cmdr.xtf (04 h ). a synch-byte ff h is automatically sent before the first byte of the xfifo will be transmitted. received data is always shifted into rfifo.
peb 2254 general functions and device architecture e1 semiconductor group 67 11.96 cyclic transmission (fully transparent) if the extended transparent mode is selected, the falc54 supports the continuous transmission of the contents of the transmit fifo. after having written 1 to 32 bytes to xfifo, the command xrep.xtf via the cmdr register (bit 7 ? 0 = 00100100 = 24 h ) forces the falc54 to repeatedly transmit the data stored in xfifo to the remote end. the cyclic transmission continues until a reset command (cmdr. sres) is issued or with resetting cmdr.xrep, after which continuous 1-s are transmitted. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. crc on/off features as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3.xcrc. receive direction the received crc checksum is always assumed to be in the 2 (crc-itu) last bytes of a frame, immediately preceding a closing flag. if ccr3.rcrc is set, the received crc checksum will be written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if hdlc mode is selected, the limits for valid frame check are modified (refer to description of bit rsis.vfr). transmit direction if ccr3.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will only be closed automatically with a (closing) flag. the falc54 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. receive address pushed to rfifo the address field of received frames can be pushed to rfifo (first one/two bytes of the frame). this function is especially useful in conjunction with the extended address recognition. it is enabled by setting control bit ccr3.radd.
peb 2254 general functions and device architecture e1 semiconductor group 68 11.96 2.2.4 time-slot assigner the falc54 offers the flexibility to extract or insert data during certain time-slots which are defined via registers rtr1-4 and ttr1-4. any combination of time-slots can be programmed independent for the receive and transmit direction. table 7 time-slot assigner time-slots receive time-slot register transmit time-slot register rtr1.7 rtr1.6 rtr1.5 rtr1.4 rtr1.3 rtr1.2 rtr1.1 rtr1.0 rtr2.7 rtr2.6 rtr2.5 rtr2.4 rtr2.3 rtr2.2 rtr2.1 rtr2.0 rtr3.7 rtr3.6 rtr3.5 rtr3.4 rtr3.3 rtr3.2 rtr3.1 rtr3.0 rtr4.7 rtr4.6 rtr4.5 rtr4.4 rtr4.3 rtr4.2 rtr4.1 rtr4.0 ttr1.7 ttr1.6 ttr1.5 ttr1.4 ttr1.3 ttr1.2 ttr1.1 ttr1.0 ttr2.7 ttr2.6 ttr2.5 ttr2.4 ttr2.3 ttr2.2 ttr2.1 ttr2.0 ttr3.7 ttr3.6 ttr3.5 ttr3.4 ttr3.3 ttr3.2 ttr3.1 ttr3.0 ttr4.7 ttr4.6 ttr4.5 ttr4.4 ttr4.3 ttr4.2 ttr4.1 ttr4.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
peb 2254 general functions and device architecture e1 semiconductor group 69 11.96 2.2.5 s a bit access the falc54 supports the s a bit signaling of time-slot 0 of every other frame in several ways. the access via registers rsw/xsw, the access via registers r/xsa8-4, capable of storing the information for a complete multiframe, and the most effective one is the access via the 64 byte deep receive/transmit fifo of the integrated signaling controller. the extended s a bit access gives the opportunity to transmit/receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. enabling is done by setting of bit ccr1.eits and resetting of registers ttr1-4, rtr1-4 and fmr1.ensa. the data written to the xfifo will subsequently transmit in the s a bit positions defined by register xc0.sa8e-4e and the corresponding bits of tswm.tsa8-4. any combination of s a bits can be selected. after the data have been completely sent out an all ones or flags (ccr1.itf) will be transmitted. the continuous transmission of a transparent bit stream, which is stored in the xfifo, can be enabled. with the setting of bit mode.hrac the received s a bits can be forwarded to the receive fifo. the access to and from the fifos is supported by isr0.rme,rpf and isr1.xpr,als.
peb 2254 general functions and device architecture e1 semiconductor group 70 11.96 2.2.6 interface to system internal highway figure 25 data on rdo
peb 2254 general functions and device architecture e1 semiconductor group 71 11.96 figure 26 data on xdi
peb 2254 general functions and device architecture e1 semiconductor group 72 11.96 figure 27 supporting signals for ccs/cas-cc applications figure 28 2-mbyte/s interface mode
peb 2254 general functions and device architecture e1 semiconductor group 73 11.96 figure 29 4-mbyte system interface mode
peb 2254 operational description e1 semiconductor group 74 11.96 3 operational description e1 reset the falc54 is forced to the reset state if a high signal is input at port res for a minimum period of 20 m s. during reset, all output stages except clk16m, clk12m, clk8m, clkx, fsc, xclk and rclk are in a high impedance state, all internal flip-flops are reset and most of the control registers are initialized with default values. after reset, the falc54 is initialized for doubleframe format with register values listed in table 8 . table 8 initial values after reset register reset value meaning fmr0 00 h nrz coding, no alarm simulation. fmr1 fmr2 00 h pcm 30 C doubleframe format, 4 mbit/s system interface mode, no ais transmission to remote end or system interface, payload loop off loop xsw xsp tswm 00 h 40 h 00 h 00 h channel loop back and single frame mode are disabled. all bits of the transmitted service word are cleared (bit 2 excl.). spare bit values are cleared. no transparent mode active xc0 xc1 00 h 00 h the transmit clock offset is cleared. the transmit time-slot offset is cleared. rc0 rc1 00 h 00 h the receive clock slot offset is cleared. the receive time-slot offset is cleared. idle icb 14 00 h 00 h idle channel code is cleared. normal operation (no idle channel selected). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, frequency on pin clkx: 2.048 mhz, no los indication on pin rclk analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm2-0 9c h ,03 h ,00 h transmit pulse mask imr1-4 ff h all interrupts are disabled rtr1-4 ttr1-4 00 h no time-slots selected
peb 2254 operational description e1 semiconductor group 75 11.96 operational phase the falc54 is programmable via a microprocessor interface which enables access to 69 control and 48 status registers. after reset the falc54 first must be initialized. general guidelines for initialization are described in section initialization. the status registers are read-only and are continuously updated. normally, the processor periodically reads the status registers to analyze the alarm status and signaling data. initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and etsi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 9 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, may be programmed simultaneously. the bit fmr1.pmod should always be kept low. mode 00 h signaling controller disabled pre rah1/2 ral1/2 00 h fd h ,ff h ff h ,ff h preamble cleared compare register for receive address cleared table 8 initial values after reset (contd) register reset value meaning
peb 2254 operational description e1 semiconductor group 76 11.96 features like channel loop back, idle channel activation, extensions for signaling support, alarm simulation, may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 hex. all control registers (except xfifo, xs1-16, cmdr, dec) are of type: read/write. table 9 initialization parameters basic set up pcm 30 mode select specification of line interface and clock generation line interface coding loss of signal detection / recovery conditions system interface mode transmit offset counters receive offset counters ais to system interface fmr1.pmod = 0 lim0, lim1, xpm2-0 fmr0.xc1/0, fmr0.rc1/0 pcd, pcr,lim1 fmr1.imod xc0.xco, xc1.xto rc0.rco, rc1.rto fmr2.dais/sais operational set up pcm 30 select framing framing additions synchronization mode signaling mode fmr2.rfs1/0, fmr1.xfs rc1.asy4, rc1.swd fmr1.afr xsp, xsw, fmr1.ensa, xsa8-4, tswm, mode, ccr1, ccr3, pre, rah1/2, ral1/2
peb 2254 operational description e1 semiconductor group 77 11.96 hdlc data transmission in transmit direction 2x32 byte fifo buffers are provided. after checking the xfifo status by polling the bit sis.xfw or after an interrupt isr1.xpr (transmit pool ready), up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can be started by issuing a xtf or xhf command via the command register. if enabled, a specified number of preambles (register pre) are optionally sent out before transmission of the current frame starts. if the transmit command does not include an end of message indication (cmdr.xme), the falc54 will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may be share a flag (enabled via ccr1.sflg), or may be transmitted as back-to-back frames, if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt isr1.xdu. the frame may be aborted per software cmdr.sres. the data transmission sequence, from the cpus point of view, is outlined in figure 30 .
peb 2254 operational description e1 semiconductor group 78 11.96 figure 30 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 31 . figure 31 interrupt driven transmission sequence example
peb 2254 operational description e1 semiconductor group 79 11.96 data reception also 2x32 byte fifo buffers are provided in receive direction. there are different interrupt indications concerned with the reception of data: hdlc rpf (receive pool full) interrupt, indicating that a 32-byte-block of data can be read from rfifo and the received message is not yet complete. rme (receive message end) interrupt, indicating that the reception of one message is completed. the following figure 32 gives an example of a reception sequence, assuming that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 32 interrupt driven reception sequence example
peb 2254 operational description e1 semiconductor group 80 11.96 3.1 detailed register description e1 3.1.1 control register description table 10 control register address arrangement address register type comment 00 xfifo w transmit fifo 01 xfifo w transmit fifo 02 cmdr w command register 03 mode r/w mode register 04 rah1 r/w receive address high 1 05 rah2 r/w receive address high 2 06 ral1 r/w receive address low 1 07 ral2 r/w receive address low 2 08 ipc r/w interrupt port configuration 09 ccr1 r/w common configuration register 1 0a ccr3 r/w common configuration register 3 0b pre r/w preamble register 0c rtr1 r/w receive timeslot register 1 0d rtr2 r/w receive timeslot register 2 0e rtr3 r/w receive timeslot register 3 0f rtr4 r/w receive timeslot register 4 10 ttr1 r/w transmit timeslot register 1 11 ttr2 r/w transmit timeslot register 2 12 ttr3 r/w transmit timeslot register 3 13 ttr4 r/w transmit timeslot register 4 14 imr0 r/w interrupt mask register 0 15 imr1 r/w interrupt mask register 1 16 imr2 r/w interrupt mask register 2 17 imr3 r/w interrupt mask register 3 18 imr4 r/w interrupt mask register 4 19 1a fmr0 r/w framer mode register 0
peb 2254 operational description e1 semiconductor group 81 11.96 1b fmr1 r/w framer mode register 1 1c fmr2 r/w framer mode register 2 1d loop r/w channel loop back 1e xsw r/w transmit service word 1f xsp r/w transmit spare bits 20 xc0 r/w transmit control 0 21 xc1 r/w transmit control 1 22 rc0 r/w receive control 0 23 rc1 r/w receive control 1 24 xpm0 r/w transmit pulse mask 0 25 xpm1 r/w transmit pulse mask 1 26 xpm2 r/w transmit pulse mask 2 27 tswm r/w transparent service word mask 28 test r/w manufacturer test register 29 idle r/w idle channel code 2a xsa4 r/w transmit sa4 bit register 2b xsa5 r/w transmit sa5 bit register 2c xsa6 r/w transmit sa6 bit register 2d xsa7 r/w transmit sa7 bit register 2e xsa8 r/w transmit sa8 bit register 2f fmr3 r/w framer mode register 3 30 icb1 r/w idle channel register 1 31 icb2 r/w idle channel register 2 32 icb3 r/w idle channel register 3 33 icb4 r/w idle channel register 4 34 lim0 r/w line interface mode 0 35 lim1 r/w line interface mode 1 36 pcd r/w pulse count detection 37 pcr r/w pulse count recovery 38 lim2 r/w line interface mode 2 table 10 control register address arrangement (contd) address register type comment
peb 2254 operational description e1 semiconductor group 82 11.96 after reset all control registers except the xfifo and xs1-16 are initialized to defined values. the status registers are only readable and are updated by the falc. 60 dec w disable error counter 62 test w manufacturer test register 70 xs1 w transmit cas register 1 71 xs2 w transmit cas register 2 72 xs3 w transmit cas register 3 73 xs4 w transmit cas register 4 74 xs5 w transmit cas register 5 75 xs6 w transmit cas register 6 76 xs7 w transmit cas register 7 77 xs8 w transmit cas register 8 78 xs9 w transmit cas register 9 79 xs10 w transmit cas register 10 7a xs11 w transmit cas register 11 7b xs12 w transmit cas register 12 7c xs13 w transmit cas register 13 7d xs14 w transmit cas register 14 7e xs15 w transmit cas register 15 7f xs16 w transmit cas register 16 table 10 control register address arrangement (contd) address register type comment
peb 2254 operational description e1 semiconductor group 83 11.96 transmit fifo (write) xfifo up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. writing data to xfifo can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following a xpr (or alls) interrupt. command register (write) value after reset: 00 h rmc receive message complete confirmation from cpu to falc54 that the current frame or data block has been fetched following a rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers will not be deleted. xrep transmission repeat if xrep is set to one together with xtf (write 24 h to cmdr), the falc54 repeatedly transmits the contents of the xfifo (1 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with a sres command or by resetting xrep. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. 7 0 xfifo xf7 xf0 (00/01) 70 cmdr rmc rres xrep xres xhf xtf xme sres (02)
peb 2254 operational description e1 semiconductor group 84 11.96 xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper will be reset. however the contents of the control registers will not be deleted. xhf transmit hdlc frame after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. xme transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the falc54 can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset the transmitter of the signaling controller will be reset. xfifo is cleared of any data and an abort sequence (seven 1's) followed by interframe time fill is transmitted. in response to xres a xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command depends on fmr1.imod. if fmr1.imod is set it takes 10 sclkx cycles and 5 sclkx cycles if fmr1.imod is cleared. therefore, if the cpu operates with a very high clock rate in comparison with the falc's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands.
peb 2254 operational description e1 semiconductor group 85 11.96 mode register (read/write) value after reset: 00 h mds2-0 mode select the operating mode of the hdlc controller is selected. 000 reserved 001 reserved 010 1 byte address comparison mode (ral1,2) 011 2 byte address comparison mode (rah1,2 and ral1,2) 100 no address comparison 101 1 byte address comparison mode (rah1,2) 110 reserved 111 no hdlc framing mode hrac hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0 receiver inactive 1 receiver active receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 ? value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. 70 mode mds2 mds1 mds0 hrac (03) 70 rah1 0 (04)
peb 2254 operational description e1 semiconductor group 86 11.96 receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1 value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. 70 rah2 (05) 70 ral1 (06) 70 ral2 (07) 70 ipc vis sci ic1 ic0 (08)
peb 2254 operational description e1 semiconductor group 87 11.96 vis masked interrupts visible 0 masked interrupt status bits are not visible. 1 masked interrupt status bits are visible. sci status change interrupt 0 interrupts will be generated either on coming or going of the internal interrupt source. 1 the following interrupts will be activated if enabled with detecting and recovering of the internal interrupt source: isr2.los; isr2.ais isr3.api; isr3.lmfa16 ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): common configuration register 1 (read/write) value after reset: 00 h sflg enable shared flags if this bit is set, the closing flag of a preceding frame simultaneously becomes the opening flag of the following frame. xts16ra transmit time-slot 16 remote alarm 0 standard operation 1 sends remote alarm in time-slot 16 towards remote end by setting the y-bit in the cas multiframe alignment word. this bit is logically ored with the contents of register xs1.2 ic1 ic0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 ccr1 sflg xts16ra casm eits itf rft1 rft0 (09)
peb 2254 operational description e1 semiconductor group 88 11.96 casm cas synchronization mode determines the synchronization mode of the channel associated signaling multiframe alignment. 0 synchronization is done in accordance to itu-t g. 732 1 synchronization is established when two consecutively correct multiframe alignment pattern are found. eits enable internal time-slot 0-31 signaling 0 internal signaling in time-slots 0-31 defined via registers rtr1- 4 or ttr1-4 is disabled. 1 internal signaling in time-slots 0-31 defined via registers rtr1- 4 or ttr1-4 is enabled. itf interframe time fill determines the idle (= no data to send) state of the transmit data coming from the signaling controller. 0 continuous logical 1 is output 1 continuous flag sequences are output (01111110 bit patterns) rft1, rft0rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after a rpf interrupt is given in the following table: the value of rft1, 0 can be changed dynamically. C if reception is not running or C after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). see note . note: it is seen that changing the value of rft1, 0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes
peb 2254 operational description e1 semiconductor group 89 11.96 after a rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by a rmc command (see table below): common configuration register 3 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. pre1, pre0 number of preamble repetition if preamble transmission is initiated, the preamble defined via register pre is transmitted 001 times 012 times 104 times 118 times. ept enable preamble transmission this bit enables transmission of a preamble. the preamble is started after interframe timefill transmission has been stopped and a new frame is to be transmitted. the preamble consists of a 8-bit pattern repeated a number of times. the pattern is defined via register pre, the number of repetitions is selected by bits pre0 and pre1. note: the shared flag feature is not influenced by preamble transmission. zero bit insertion is disabled during preamble transmission. rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc4 . 0 rbc3 0 rbc1,0 rbc0 70 ccr3 pre1 pre0 ept radd rcrc xcrc (0a)
peb 2254 operational description e1 semiconductor group 90 11.96 radd receive address pushed to rfifo if this bit is set to 1, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode. rcrc receive crc on/off only applicable in non-auto mode. if this bit is set to 1, the received crc checksum will be written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for valid frame check are modified ( refer to rsis.vfr ). xcrc transmit crc on/off if this bit is set to 1, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo). the transmitted frame will be closed automatically with a closing flag. note: the falc54 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. preamble register (read/write) value after reset: 00 h pre0...pre7... preamble register this register defines the pattern which is sent out during preamble transmission (refer to register ccr3). lsb is sent first. note: it should be taken into consideration that zero bit insertion is disabled during preamble transmission. 70 pre pre7 pre0 (0b)
peb 2254 operational description e1 semiconductor group 91 11.96 receive timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 timeslot register these bits define the received channels (time-slots) to be extracted. additionally this registers will control the rsigm marker which can be forced high during the respective time-slots independent of bit ccr1.eits. a one in the rtr1-4 bits will sample the corresponding time-slot from the data which are output on pin rdo, if bit ccr1.eits is set. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? normal operation. 1 the contents of the selected time-slot will be stored in the rfifo. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (0f)
peb 2254 operational description e1 semiconductor group 92 11.96 transmit timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 transmit timeslot register these bits define the transmit channels (time-slots) to be inserted. additionally this registers will control the xsigm marker which can be forced high during the respective time-slots independent of bit ccr1.eits. a one in the ttr1-4 bits will insert the corresponding time-slot in the data received on pin xdi, if bit ccr1.eits is set. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? normal operation. 1 the contents of the selected time-slot will be inserted in the outgoing data stream. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (13)
peb 2254 operational description e1 semiconductor group 93 11.96 interrupt mask register 0 ... 4 value after reset: ff h , ff h , ff h , ff h , ff h imr0...imr4... interrupt mask register each interrupt source can generate an interrupt signal at port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr0 ... 4 sets the mask active for the interrupt status in isr0 ... 3. masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. note: after reset, all interrupts are dis abled. framer mode register 0 (read/write) value after reset: 00 h xc1... xc0 transmit code serial code transmitter is different programmable from the receiver. 00... nrz (optical interface) 01... cmi (1t2b + hdb3), (optical interface) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) 70 imr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (14) imr1 rdo alls xdu xmb xlsc xpr (15) imr2 far lfa mfar t400ms ais los rar ra (16) imr3 es sec lmfa16 ais16 ra16 api sln slp (17) imr4 lfa fer cer ais los cve slip ebe (18) 70 fmr0 xc1 xc0 rc1 rc0 extd alm frs sim (1a)
peb 2254 operational description e1 semiconductor group 94 11.96 rc1... rc0 receive code serial code receiver is different programmable from the transmitter. 00... nrz (optical interface) 01... cmi (1t2b+hdb3), (optical interface) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) extd extended hdb3 error detection selects error detection mode. 0 only double violations are detected. 1 extended code violation detection: 0000 strings are detected additionally. thereafter, incrementation of code violation counter cvc is first done after receiving an additional four zeros. alm alarm mode selects the ais alarm detection mode. 0 ... the ais alarm will be detected according to ets300233. detection: an ais alarm will be detected if the incoming data stream contains less than 3 zeros within a period of 512 bits and a loss of frame alignment is indicated. recovery: the alarm will be cleared if 3 or more zeros within 512 bits will be detected or the fas word is found. 1 ... the ais alarm will be detected according to itu-t g.775 detection: an ais alarm will be detected if the incoming data stream contains for two consecutive doubleframe periods (1024 bits) less than 3 zeros for each doubleframe period (512 bits). recovery: the alarm will be cleared if within two consecutive doubleframe periods 3 or more zeros for each period of 512 bits will be detected. frs force resynchronization a transition from low to high will initiate a resynchronization procedure of the pulse frame and the crc-multiframe (if enabled via bit fmr2.rfs1) starting directly after the old framing candidate.
peb 2254 operational description e1 semiconductor group 95 11.96 sim alarm simulation 0 normal operation. 1 initiates internal error simulation of ais, loss of signal, loss of synchronization, auxiliary pattern indication, slip, framing errors, crc errors, and code violations. the error counters fec, cvc, cec1 will be incremented. framer mode register 1 (read/write) value after reset: 00 h mfcs multiframe force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0=10). a transition from low to high will initiate the resynchronization procedure for crc-multiframe alignment without influencing doubleframe synchronous state. in case, automatic force resynchronization (fmr1.afr) is enabled and multiframe alignment can not be regained, a new search of doubleframe (and crc multiframe) is automatically initiated. afr automatic force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0=10). if this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe patterns with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained or command fmr1.mfcs has been issued. ensa enable s a -bit access via register xsa4-8 only applicable if fmr1.xfs is set to one. 0 normal operation. the s a -bit information will be taken from bits xsw.xy04 and written to bits rsw.ry04. 1 s a -bit register access. the s a -bit information will be taken from the registers xsa4-8. in addition, the received information will be written to registers rsa4-8. transmitting contents of registers xsa4-8 will be disabled if one of time-slot 0 transparent modes is enabled (xsp.tt0 or tswm.sa4-8). 70 fmr1 mfcs afr ensa pmod xfs ecm imod xais (1b)
peb 2254 operational description e1 semiconductor group 96 11.96 pmod pcm mode for e1 application this bit must be set low. 0... pcm30 mode. 1... pcm24 mode. xfs transmit framing select selection of the transmit framing format could be done independent of the receive framing format. 0 doubleframe format enabled. 1 crc4-multiframe format enabled. ecm error counter mode the function of the error counters will be determined by this bit. 0 ? before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters will be reset with the rising edge of the corresponding bits in the dec register. 1 every second the error counter will be latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided. imod system interface mode 0 4 mbit/s mode. 1 2 mbit/s mode. xais transmit ais towards remote end sends ais via ports xl1, xl2, xoid towards the remote end. the outgoing data stream which could be looped back via the local loop to the system interface will not be affected.
peb 2254 operational description e1 semiconductor group 97 11.96 framer mode register 2 (read/write) value after reset: 00 h rfs1... rfs0... receive framing select 00 ... doubleframe format 01 ... doubleframe format 10 ... crc4 multiframe format 11 ... crc4 multiframe format with modified crc4 multiframe alignment algorithm (interworking according to itu-t g.706 annex b). setting of fmr3.extiw changes the reaction after the 400 msec timeout. rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the disable ais to system interface feature (fmr2.dais) to realize undisturbed transparent reception. dais disable ais to system interface 0 ais is automatically inserted into the data stream to rdo if falc54 is in asynchronous state. 1 automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais send ais towards system interface sends ais via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loopback 0 normal operation 1... the payload loopback will loop the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received at port xdi, sypx and xmfs will be ignored. with xsp.tt0=1 timeslot 0 will also be looped. if xsp.tt0=0 timeslot 0 will be generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. 70 fmr2 rfs1 rfs0 rtm dais sais plb axra almf (1c)
peb 2254 operational description e1 semiconductor group 98 11.96 axra automatic transmit remote alarm 0 ... normal operation 1 ... the remote alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be reset. additionally in multiframe format fmr2.rfs1=1 and fmr3.extiw =1 and the 400 msec timeout has elapsed, the remote alarm bit will be active in the outgoing data stream. in multiframe synchronous state the outgoing remote alarm bit is cleared. almf automatic loss of multiframe 0 ... normal operation 1 ... the receiver will search a new basic- and multiframing if more than 914 crc errors have been detected in a time interval of one second. the internal 914 crc error counter will be reset if the multiframe synchronization is found. incrementing the counter is only enabled in the multiframe synchronous state. channel loop back (read/write) value after reset: 00 h sfm single frame mode setting this bit reduces the receive speech memory from two to one frame length. in this case, clocks sclkr and rclk have to be phase locked to avoid slip conditions. however, slip detection still works but without any influence on data transmission. eclb enable channel loop back 0 ... disables the channel loop back. 1 ... enables the channel loop back selected by this register. cla4cla0 channel address for loop back cla = 031 selects the channel. during looped back the contents of the assigned outgoing channel at ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed at register idle. 70 loop sfm eclb cla4 cla0 (1d)
peb 2254 operational description e1 semiconductor group 99 11.96 transmit service word pulseframe (read/write) value after reset: 00 h xsis spare bit for international use first bit of the service word. only significant in doubleframe format. if not used, this bit should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bit xsp.tt0, or tswm.tsis), bit xsw.xsis will be ignored. xra transmit remote alarm 0 normal operation. 1 sends remote alarm towards remote end by setting bit 3 of the service word. if time-slot 0 transparent mode is enabled via bit xsp.tt0 or tswm.tra bit is set, bit xsw.xra will be ignored. xy0xy4 spare bits for national use (y-bits, s n -bits, s a -bits) these bits are inserted in the service word of every other pulseframe if s a -bit register access is disabled (fmr1.ensa = 0). if not used, they should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bit xsp.tt0 or tswm.tsa4-8), bits xsw.xy04 will be ignored. transmit spare bits (read/write) value after reset: 00 h xap transmit auxiliary pattern towards remote end 0 normal operation. 1 a one in this bit position will cause the transmitter to send an alternating pattern 101010... towards the remote end. fmr1.xais = 1 will overwrite the alternating pattern by a continuous one bitstream. 70 xsw xsis xra xy0 xy1 xy2 xy3 xy4 (1e) 70 xsp xap casen tt0 ebp axs xsif xs13 xs15 (1f)
peb 2254 operational description e1 semiconductor group 100 11.96 casen channel associated signaling enable 0 normal operation. 1 a one in this bit position will cause the transmitter to send the cas information stored in the xs1-16 registers in the corresponding time slots. tt0 time-slot 0 transparent mode 0 normal operation. 1 all information for time-slot 0 at port xdi will be inserted in the outgoing pulseframe. all internal information of the falc54 (framing, crc, s a /s i bit signaling, remote alarm) will be ignored. this function is mainly useful for system test applications (test loops). priority sequence of transparent modes: xsp.tto > tswm. ebp e- bit polarity 0 in the basic - or multiframe asynchronous state the e-bit will be set to zero. 1 in the basic - or multiframe asynchronous state the e-bit will be set to one. if automatic transmission of sub-multiframe status is enabled by setting bit xsp.axs and the receiver has been lost multiframe synchronization, the e bit with the programmed polarity will be inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time-slot 0 transparent mode and transparent si bit in service word are both disabled). axs automatic transmission of submultiframe status only applicable to crc multiframe. 0 normal operation. 1 information of submultiframe status bits rsp.si1 and rsp.si2 will be automatically inserted in s i -bit positions of the outgoing crc multiframe (rsp.si1 ? s i -bit of frame 13; rsp.si2 ? s i -bit of frame 15). contents of xsp.xs13 and xsp.xs15 will be ignored. if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.axs has no function.
peb 2254 operational description e1 semiconductor group 101 11.96 xsif transmit spare bit for international use (fas word) first bit in the fas word. only significant in doubleframe format. if not used, this bit should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bits xsp.tt0, or tswm.tsif), bit xsp.xsif will be ignored. xs13 transmit spare bit (frame 13, crc-multiframe) first bit in the service word of frame 13 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to 1. the information of xsp.xs13 will be shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit xsp.axs, or, if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.xs13 will be ignored. xs15 transmit spare bit (frame 15, crc-multiframe) first bit in the service word of frame 15 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to 1. the information of xsp.xs15 will be shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit xsp.axs, or, if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsif is enabled, bit xsp.xs15 will be ignored. transmit control 0 (read/write) value after reset: 00 h sa8esa4e sa bit signaling enable 0 standard operation. 1 setting this bit it will be possible to send / receive a lapd protocol in any combination of the sa8- sa4 bit positions in the outgoing / incoming data stream. the on chip signaling controller has to be configured in the hdlc/lapd mode. in transmit direction together with these bits the tswm.tsa8-4 bits must be set to enable transmission to the remote end transparently through the falc. 70 xc0 sa8e sa7e sa6e sa5e sa4e xco2 xco1 xco0 (20)
peb 2254 operational description e1 semiconductor group 102 11.96 xco2xco0 transmit clock slot offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse at port sypx is active (see figure 26 ). transmit control 1 (read/write) value after reset: 00 h xcos transmit clock offset shift 0 the delay t between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is an even number in the range from 0 to 1022 sclkx cycles. 1 the delay t is an odd number in the range from 1 to 1023 sclkx cycles. xto5xto0 transmit time-slot offset initial value loaded into the transmit time-slot counter at the trigger edge of sclkx when the synchronous pulse at port sypx is active (see figure 26 ). receive control 0 (read/write) value after reset: 00 h rcos receive clock offset shift 0 the delay t between the beginning of time-slot 0 and the initial edge of sclkr (after sypr goes active) is an even number in the range from 0 to 1022 sclkr cycles. 1 the delay t is an odd number in the range from 1 to 1023 sclkr cycles. 70 xc1 xcos xto5 xto0 (21) 70 rc0 rcos sics crci xcrci rdis rco2 rco1 rco0 (22)
peb 2254 operational description e1 semiconductor group 103 11.96 sics system interface channel select only applicable if bit fmr1.imod (4 mhz system interface) is set. 0 received data is output on port rdo in the first channel phase. data in the second channel phase is tri-stated. data on pin xdi is sampled only in the first channel phase. data in the second channel phase is ignored. 1 data on port rdo is output in the second channel phase. the first channel phase is tri-stated. sampling of data from the system highway is done in the second channel phase. crci automatic crc4 bit inversion if set, all crc bits of one outgoing submultiframe are inverted in case a crc error is flagged for the previous received submultiframe. this function is logically ored with rc0.xcrci. xcrci transmit crc4 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense 0 inputs: rdip, rdin active low, input roid is active high 1 inputs: rdip, rdin active high, input roid is active low rco2rco0 receive clock-slot offset initial value which is loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 25 ). receive control 1 (read/write) value after reset: 00 h swd service word condition disable 0 standard operation. three or four consecutive incorrect service words (depending on bit rc1.asy4) will cause loss of synchronization. 70 rc1 swd asy4 rto5 rto0 (23)
peb 2254 operational description e1 semiconductor group 104 11.96 1 errors in service words have no influence when in synchronous state. however, they are used for the resynchronization procedure. asy4 select loss of sync condition 0 standard operation. three consecutive incorrect fas words or three consecutive incorrect service words will cause loss of synchronization. 1 four consecutive incorrect fas words or four consecutive incorrect service words will cause loss of synchronization. the service word condition may be disabled via bit rc1.swd. rto5rto0 receive time-slot offset initial value which is loaded into the receive time-slot counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 25 ). transmit pulse-mask 2...0 (read/write) value after reset: 9c h , 03 h , 00 h the transmit pulse shape which is defined in itu-t g.703 will be output on pins xl1 and xl2. the level of the pulse shape can be programmed via registers xpm2-0 to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape will be internally devided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value will define the level of the analog voltage on pins xl1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape. the four 5 bit values will be sent in the following sequence: xp04-00: first pulse shape level xp14-10: second pulse shape level xp24-20: third pulse shape level xp34-30: fourth pulse shape level 70 xpm0 xp12 xp11 xp10 xp04 xp03 xp02 xp01 xp00 (24) xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (25) xpm2 xlhp xlt daxlt xp34 xp33 xp32 xp31 (26)
peb 2254 operational description e1 semiconductor group 105 11.96 changing the lsb of each subpulse in registers xpm2-0 will change the amplitude of the differential voltage on xl1/2 by approximately 110 mv. example: 120 w interface and wired as shown in figure 15 . xpm04-00: 1d h xpm14-10: 1d h xpm24-20: 00 h xpm34-30: 00 h programming values for xpm0-2: bd h , 03 h , 00 h xlhp transmit line high power 0 ... normal operation. 1 ... with this bit the output current capability of the transmit line xl1 and xl2 can be influenced. connecting low impedances to the outputs xl1/xl2 this bit should be set to one to avoid instable pulse shapes. setting this bit has no influence on the voltage levels of the pulse shape. xlt transmit line tri-state 0 normal operation 1 transmit line xl1/xl2 or xdop/xdon are switched into high impedance state. if this bit is set the transmit line monitor status information will be frozen. daxlt... disable automatic tristating of xl1/2 0... normal operation. if a short is detected on pins xl1/2 the transmit line monitor will set the xl1/2 outputs into a high impedance state. 1... if a short is detected on xl1/2 pins automatic setting these pins into a high impedance (by the xl-monitor) state will be disabled.
peb 2254 operational description e1 semiconductor group 106 11.96 transparent service word mask (read/write) value after reset: 00 h tswm7tswm0transparent service word mask tsis transparent si bit in service word 0 the si bit will be generated internally. 1 the si bit in the service word will be taken from port xdi and transparently passed through the falc54 without any changes. the internal information of the falc54 (register xsw) will be ignored. tsif transparent si bit in fas word 0 the si bit will be generated internally. 1 the si bit in the fas word will be taken from port xdi and routed transparently through the falc54 without any changes. the internal information of the falc54 (register xsw) will be ignored. tra transparent remote alarm 0 the remote alarm bit will be generated internally. 1 the a bit will be taken from port xdi and routed transparently through the falc54 without any changes. the internal information of the falc54 (register xsw) will be ignored. tsa4tsa8... transparent sa4...8 bit 0 the sa4-8 bit will be generated internally. 1 the sa4-8 bit will be taken from port xdi or from the internal signaling controller if enabled and transparently passed through the falc54 without any changes. the internal information of the falc54 (registers xsw and xsa4-8) will be ignored. 70 tswm tsis tsif tra tsa4 tsa5 tsa6 tsa7 tsa8 (27)
peb 2254 operational description e1 semiconductor group 107 11.96 idle channel code register (read/write) value after reset: 00 h idl7idl0 idle channel code if channel loop back is enabled by programming loop.eclb=1, the contents of the assigned outgoing channel at ports xl1/xl2 resp. xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels selected via the idle channel registers icb1icb4. idl7 will be transmitted first. transmit sa4-8 register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h , 00 h xsa8xsa4 transmit s a -bit data the sa-bit register access is enabled by setting bits fmr1.xfs = 1 and fmr1.ensa = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xsa4-8 will be copied into a shadow register. the contents will subsequently sent out in the service words of the next outgoing crc multiframe (or doubleframes) if none of the time-slot 0 transparent modes is enabled. xs40 will be sent out in bit position 4 in frame 1, xs47 in frame 15. the transmit multiframe begin interrupt xmb request that these registers should be serviced. if requests for new information are ignored, current contents will be repeated. 70 idle idl7 idl0 (29) 70 xsa4 xs47 xs46 xs45 xs44 xs43 xs42 xs41 xs40 (2a) xsa5 xs57 xs56 xs55 xs54 xs53 xs52 xs51 xs50 (2b) xsa6 xs67 xs66 xs65 xs64 xs63 xs62 xs61 xs60 (2c) xsa7 xs77 xs76 xs75 xs74 xs73 xs72 xs71 xs70 (2d) xsa8 xs87 xs86 xs85 xs84 xs83 xs82 xs81 xs80 (2e)
peb 2254 operational description e1 semiconductor group 108 11.96 framer mode register 3 (read/write) value after reset: 00 h cmi select cmi precoding only valid if cmi code (fmr0.xc1/0=01) is selected. this bit defines the cmi precoding and influences only the transmit data and not the receive data. 0 cmi with hdb3 precoding 1 cmi without hdb3 precoding sa6sy receive sa6 access synchron mode only valid if multiframe format (fmr2.rfs1/0=1x) is selected. 0 the detection of the predefined sa6 bit pattern (refer to chapter sa6 bit detection according to ets 300233) is done independently of the multiframe synchronous state. 1 the detection of the sa6 bit pattern is done synchronously to the multiframe. cfrz enable cas freeze output this bit selects the function of pin rfspq. 0 the receive frame synchron pulse is output on pin rfspq. 1 the synchronous status of the integrated cas controller (frs1.ts16lfa) is output on pin rfspq. if the cas synchronizer lost its synchronization this pin is set high. extiw extended crc4 to non crc4 interworking only valid in multiframe format. this bit selects the reaction of the synchronizer after the 400 msec timeout has been elapsed and starts transmitting a remote alarm if fmr2.axra is set. 0 the crc4 to non crc4 interworking is done as described in itu-t g. 706 annex b. 1 the interworking is done according to itu-t g. 706 with the exception that the synchronizer will still search the multiframing even if the 400 msec timer is expired. switching into doubleframe format is disabled. if fmr2.axra is set the remote alarm bit will be active in the outgoing data stream. 70 fmr3 cmi sa6sy cfrz extiw 2f
peb 2254 operational description e1 semiconductor group 109 11.96 idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic1ic32 idle channel selection bits these bits define the channels (time-slots) of the outgoing pcm frame to be altered. assignments: ic0 ? time-slot 0 ic1 ? time-slot 1 ic31 ? time-slot 31 0 normal operation. 1 idle channel mode. the contents of the selected time-slot is overwritten by the idle channel code defined via register idle. note: although time-slot 0 can be selected via bit ic0, its contents is only altered if the transparent mode is selected (xsp.tt0). line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode 0output signals xdop/xdon are half bauded (normal operation). 1output signals xdop/xdon are full bauded. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. 70 icb1 ic0 ic1 ic2 ic3 ic4 ic5 ic6 ic7 (30) icb2 ic8 ic9 ic10 ic11 ic12 ic13 ic14 ic15 (31) icb3 ic16 ic17 ic18 ic19 ic20 ic21 ic22 ic23 (32) icb4 ic24 ic25 ic26 ic27 ic28 ic29 ic30 ic31 (33) 70 lim0 xfb xdos scl1 scl0 eqon elos ll mas (34)
peb 2254 operational description e1 semiconductor group 110 11.96 xdos transmit data out sense 0 output signals xdop/xdon are active low. output xoid is active high (normal operation). 1 output signals xdop/xdon are active high. output xoid is active low. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. scl1 ... scl0 select clock output 00 output frequency at pin clkx: 2048 khz active high 01 output frequency at pin clkx: 2048 khz active low 10 output frequency at pin clkx: 4096 khz active high 11 output frequency at pin clkx: 4096 khz active low eqon receive equalizer on 0 6 db receiver: equalizer off 1 18 db equalizer on elos enable loss of signal 0... normal operation. the extracted receive clock is output via pin rclk. 1... in case of loss of signal (frs0.los=1) the rclk is set high. if frs0.los=0 the received clock is output via rclk. ll local loop 0 normal operation 1 local loop active. the local loopback mode disconnects the receive lines rl1/rl2 resp. rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream will be undisturbed transmitted on the line. receiver and transmitter coding must be identical.
peb 2254 operational description e1 semiconductor group 111 11.96 mas master mode 0 slave mode 1 master mode on. if this bit is set and the sync pin is connected to v ss the falc54 works as a master for the system. the internal dcos of the jitter attenuator are centered and the system clocks which are output via clk8m/clkx are stable (divided from the dco frequencies). if a clock (2.048 mhz) is detected at the sync pin the falc54 synchronizes automatically to this clock. the production tolerance is approximately 30 ppm of the crystal frequency if c load = 15 pf. line interface mode 1 (read/write) value after reset: 00 h efsc enable frame synchronization pulse 0 ... the transmit clock is output via pin xclk. 1 ... pin xclk provides a 8 khz frame synchronization pulse which is active high for one 2 mhz cycle (pulse width = 488 ns). ril2ril0 receive input threshold only valid if analog line interface is selected (lim1.drs=0). no signal will be declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2-0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal will be declared is programmable via the ril2-0 bits. differential input voltage between pins rl1/2: 000 = 1.36 v 001 = 1.04 v 010 = 0.84 v 011 = 0.62 v 100 = 0.43 v 101 = 0.32 v 110 = 0.22 v 111 = not assigned 70 lim1 efsc ril2 ril1 ril0 jatt rl drs (35)
peb 2254 operational description e1 semiconductor group 112 11.96 jattrl... transmit jitter attenuator / remote loop 00 ... normal operation. the transmit jitter attenuator is disabled. transmit data will bypass the buffer. 01 ... remote loop active without transmit jitter attenuator enabled. transmit data will bypass the buffer. 10 ... transmit slicer active. transmit data received on port xdi from the system highway will be first written into the transmit jitter attenuator and then sent jitter free on ports xl1/2 or xdop/n or xoid. 11 ... remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid will be sent jitter free on ports xl1/2 or xdop/n or xoid. drs dual rail select 0 ... the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 ... the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon. pulse count detection register (read/write) value after reset: 00 h pcd7pcd0 pulse count detection a los alarm will be detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and can be calculated as follows: t= 16(n+1) ; with 0 =< n =< 255. the maximum time is: 256 x 16 x 488 ns = 2 ms. every detected pulse will reset the internal pulse counter. the counter will be clocked with the receive clock rclk. 70 pcd pcd7 pcd0 (36)
peb 2254 operational description e1 semiconductor group 113 11.96 pulse count recovery (read/write) value after reset: 00 h pcr7pcr0 pulse count recovery a los alarm will be cleared if a pulse density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n+1 ; with 0 =< n =< 255. the time interval starts with the first detected pulse transition. with every received pulse a counter will be incremented and the actual counter is compared with the contents of pcr register. if the pulse number >= the pcr value the los alarm will be reset otherwise the alarm will still be active. in this case the next detected pulse transition will start a new time interval. additional loss of signal recovery conditions may be selected by register lim2.los2/1. line interface mode 2 (read/write) value after reset: 00 h los2/1 loss of signal recovery condition 00 the los alarm will be cleared if the predefined pulse density by register pcr is detected during the time interval which is defined by register pcd. 01 additionally to the recovery condition described above a los alarm will only be cleared if the pulse density is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval. 10 clearing a los alarm will be done if the pulse density is fulfilled and no more than 99 contiguous zeros are detected during the recovery interval. 11 not assigned 70 pcr pcr7 pcr0 (37) 70 lim2 los2 los1 (38)
peb 2254 operational description e1 semiconductor group 114 11.96 disable error counter (write) value after reset: 00 h dcec3 disable crc error counter 3 only valid if fmr1.ecm is reset. this bit has to be set before reading the crc error counter 3. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the crc error counter is latched and then cleared. dcec2 disable crc error counter 2 only valid if fmr1.ecm is reset. this bit has to be set before reading the crc error counter 2. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the crc error counter is latched and then cleared. dcec1 disable crc error counter 1 only valid if fmr1.ecm is reset. this bit has to be set before reading the crc error counter 1. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the crc error counter is latched and then cleared. debc disable e-bit error counter only valid if fmr1.ecm is reset. this bit has to be set before reading the e-bit error counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the e-bit error counter is latched and then cleared. dcvc disable code violation counter only valid if fmr1.ecm is reset. this bit has to be set before reading the code violation counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the code violation counter is latched and then cleared. 70 dec dcec3 dcec2 dcec1 debc dcvc dfec (60)
peb 2254 operational description e1 semiconductor group 115 11.96 dfec disable framing error counter only valid if fmr1.ecm is reset. this bit has to be set before reading the framing error counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the framing error counter is latched and then cleared.
peb 2254 operational description e1 semiconductor group 116 11.96 transmit cas register (write) value after reset: not defined transmit cas register 1-16 the transmit cas register access is enabled by setting bit xsp.casen = 1. each register except xs1 contains the cas bits for two timeslots. with the transmit multiframe begin isr1.xmb the contents of these registers will be copied into a shadow register. the contents will subsequently sent out in the timeslots 16 of the outgoing data stream. xs1.7 will be sent out first and xs16.0 will be sent last. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information are ignored, current contents will be repeated. xs1 has to be programmed with the multiframe pattern. this pattern should always stay low otherwise the remote end will lose its synchronization. with setting the y-bit a remote alarm will be transmitted to the far end. the y-bit is logically ored with bit ccr1.xts16ra. the x bits (spare bits) should be set to one if they are not used. 70 xs1 0 0 0 0 x y x x (70) xs2 a1 b1 c1 d1 a16 b16 c16 d16 (71) xs3 a2 b2 c2 d2 a17 b17 c17 d17 (72) xs4 a3 b3 c3 d3 a18 b18 c18 d18 (73) xs5 a4 b4 c4 d4 a19 b19 c19 d19 (74) xs6 a5 b5 c5 d5 a20 b20 c20 d20 (75) xs7 a6 b6 c6 d6 a21 b21 c21 d21 (76) xs8 a7 b7 c7 d7 a22 b22 c22 d22 (77) xs9 a8 b8 c8 d8 a23 b23 c23 d23 (78) xs10 a9 b9 c9 d9 a24 b24 c24 d24 (79) xs11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) xs12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) xs13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) xs14 a13 b13 c13 d13 a28 b28 c28 d28 (7d) xs15 a14 b14 c14 d14 a29 b29 c29 d29 (7e) xs16 a15 b15 c15 d15 a30 b30 c30 d30 (7f)
peb 2254 operational description e1 semiconductor group 117 11.96 3.1.2 status register address arrangement address write type comment 00/01 rfifo r receive fifo 4c frs0 r framer receive status 0 4d frs1 r framer receive status 1 4e rsw r receive service word 4f rsp r receive spare bits 50 fecl r framing error counter low 51 fech r framing error counter high 52 cvcl r code violation counter low 53 cvch r code violation counter high 54 cec1l r crc error counter 1 low 55 cec1h r crc error counter 1 high 56 ebcl r e-bit error counter low 57 ebch r e-bit error counter high 58 cec2l r crc error counter 2 low 59 cec2h r crc error counter 2 high 5a cec3l r crc error counter 3 low e1: status register address arrangement (contd) address write type comment 5b cec3h r crc error counter 3 high 5c rsa4 r receive sa4 bit register 5d rsa5 r receive sa5 bit register 5e rsa6 r receive sa6 bit register 5f rsa7 r receive sa7 bit register 60 rsa8 r receive sa8 bit register 61 rsa6s r receive sa6 bit status register 62 tsr0 r manufacturer test register 63 tsr1 r manufacturer test register 64 sis r signaling status register 65 rsis r receive signaling status register
peb 2254 operational description e1 semiconductor group 118 11.96 66 rbcl r receive byte control low 67 rbch r receive byte control high 68 isr0 r interrupt status register 0 69 isr1 r interrupt status register 1 6a isr2 r interrupt status register 2 6b isr3 r interrupt status register 3 6c 6d 6e gis r global interrupt status 6f vstr r version status 70 rs1 r receive cas register 1 71 rs2 r receive cas register 2 72 rs3 r receive cas register 3 73 rs4 r receive cas register 4 74 rs5 r receive cas register 5 75 rs6 r receive cas register 6 76 rs7 r receive cas register 7 77 rs8 r receive cas register 8 78 rs9 r receive cas register 9 79 rs10 r receive cas register 10 7a rs11 r receive cas register 11 7b rs12 r receive cas register 12 7c rs13 r receive cas register 13 7d rs14 r receive cas register 14 7e rs15 r receive cas register 15 7f rs16 r receive cas register 16 e1: status register address arrangement (contd) address write type comment
peb 2254 operational description e1 semiconductor group 119 11.96 receive fifo (read) rfifo reading data from rfifo can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft 1 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the receive message complete command (rmc). framer receive status register 0 (read) los loss of signal detection: this bit is set when the incoming signal has no transitions (analog interface) or logical zeros (dig. interface) in a time interval of t consecutive pulses, where t is programmable via pcd register. total account of consecutive pulses: 1 6 peb 2254 operational description e1 semiconductor group 120 11.96 recovery: analog interface: the bit will be reset when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril2-0) for at least m pulse periods defined by register pcr in the pcd time interval. digital interface: the bit will be reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) will be set. for additionally recovery conditions refer also to register lim2.los2/1. the bit will also be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. ais alarm indication signal the function of this bit is determined by fmr0.alm. fmr0.alm = 0: this bit is set when two or less zeros in the received bit stream are detected in a time interval of 250 m s and the falc54 is in the asynchronous state (frs0.lfa = 1). the bit will be reset when no alarm condition is detected (etsi). fmr0.alm = 1: this bit is set when the incoming signal has two or less zeros in each of two consecutive double frame periods(512 bits). this bit will be cleared when each of two consecutive doubleframe periods contain three or more zeros or when the frame alignment signal fas has been found. (itu-t: g.775) the bit will also be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. with the rising edge of this bit an interrupt status bit (isr2.ais) will be set. lfa loss of frame alignment this bit is set after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (can be disabled). with the rising edge of this bit an interrupt status bit (isr2.lfa) will be set. the specification of the loss of sync conditions is done via bits rc1.swd and rc1.asy4. after loss of synchronization, the frame aligner will resynchronize automatically.
peb 2254 operational description e1 semiconductor group 121 11.96 the following conditions have to be detected to regain synchronous state: C the presence of the correct fas word in frame n. C the presence of the correct service word (bit 2 = 1) in frame n + 1. C for a second time the presence of a correct fas word in frame n+2. the bit is cleared when synchronization has been regained (directly after the second correct fas word of the procedure described above has been received). if the crc-multiframe structure is enabled by setting bit fmr2.rfs1, multiframe alignment is assumed to be lost if pulse-frame synchronization has been lost. the resynchronization procedure for multiframe alignment starts after the bit frs0.lfa has been cleared. multiframe alignment has been regained if two consecutive crc- multiframes have been received without a framing error (refer to frs0.lmfa). the bit will be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. if bit frs0.lfa is cleared a loss of frame alignment recovery interrupt status isr2.far will be generated. rra receive remote alarm set if bit 3 of the received service word is set. an alarm interrupt status isr2.ra can be generated if the alarm condition is detected. frs0.rra will be cleared when no alarm is detected. at the same time a remote alarm recovery interrupt status isr2.rar will be generated. the bit rsw.rra has the same function. both status and interrupt status bits will be set during alarm simulation. auxp auxiliary pattern indication this bit is set when 254 or more 10 are received in a time interval of 250 m s and the frame alignment is lost frs0.lfa = 1. an interrupt status isr3.api will be generated if this bit is set. the bit will be reset when no auxiliary pattern condition is detected. the bit will also be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists.
peb 2254 operational description e1 semiconductor group 122 11.96 nmf no multiframe alignment found this bit is only valid if the crc4 interworking is selected (fmr2.rfs1/0 = 11). set if the multiframe pattern could not be detected in a time interval of 400 msec after the framer has reached the doubleframe synchronous state. the receiver is then automatically switched to doubleframe format. this bit is reset if the basic framing has been lost. lmfa loss of multiframe alignment not used in doubleframe format (fmr2.rfs1 = 0). in this case, set to logical 1. in crc-multiframe mode (fmr2.rfs1 = 1), this bit is set C if force resynchronization is initiated by setting bit fmr0.frs, or C if multiframe force resynchronization is initiated by setting bit fmr1.mfcs, or C if pulseframe alignment has been lost (frs0.lfa). it is reset if two crc-multiframes have been received at an interval of n 2 ms (n = 1, 2, 3) without a framing error. if bit frs0.lmfa is cleared a loss of multiframe alignment recovery interrupt status isr2.mfar will be generated. framer receive status register 1 (read) ts16ra receive timeslot 16 remote alarm this bit contains the actual information of the received remote alarm bit rs1.2 in time-slot 16. setting and resetting of this bit will cause an interrupt status change isr3.ra16. ts16los receive timeslot 16 loss of signal this bit is set if the incoming ts16 data stream contains always zeros for at least 16 contiguously received time-slots. a one in a time-slot 16 will reset this bit. 7 0 frs1 ts16ra ts16los ts16ais ts16lfa xls xlo (4d)
peb 2254 operational description e1 semiconductor group 123 11.96 ts16ais receive timeslot 16 alarm indication signal the detection of the alarm indication signal in timeslot 16 is according to itu-t g.775. this bit is set if the incoming ts16 contains less than 4 zeros in each of two consecutive ts16 multiframe periods. this bit will be cleared if two consecutive received cas multiframe periods contains more than 3 zeros or the multiframe pattern was found in each of them. this bit will be cleared if ts0 synchronization is lost. ts16lfa receive timeslot 16 loss of multiframe alignment 0 ... the cas controller is in synchronous state after frame alignment is accomplished. 1 ... this bit is set if the framing pattern 0000 in 2 consecutive cas multiframes were not found or in all ts16 of the preceding multiframe all bits were reset. an interrupt isr3.lmfa16 will be generated. xls transmit line short significant only if the ternary line interface is selected by lim1.drs=0. 0 normal operation. no short is detected. 1 the xl1 and xl2 are shortend for at least 32 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high impedance state if bit xpm2.daxlt is reset. after 32 consecutive pulse periods the outputs xl1/2 are activated again until the first pulse is transmitted. if a short between xl1/2 is still further active the outputs xl1/2 are in high impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit will be reset. with any change of this bit an interrupt isr1.xlsc will be generated. in case of xpm2.xlt is set this bit will be frozen. xlo transmit line open 0 normal operation 1 this bit will be set if at least 32 consecutive zeros were sent via pins xl1/xl2 resp. xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc will be set. in case of xpm2.xlt is set this bit will be frozen.
peb 2254 operational description e1 semiconductor group 124 11.96 receive service word pulseframe (read) rsi receive spare bit for international use first bit of the received service word. it is fixed to one if crc- multiframe mode is enabled. rra receive remote alarm equivalent to bit frs0.rra. ry0ry4 receive spare bits for national use (y-bits, sn-bits, sa-bits) receive spare bits/additional status (read) si1si2 submultiframe error indication 1, 2 not valid if doubleframe format is enabled. in this case, both bits are set to logical 1. when using crc-multiframe format these bits are set to 0 if multiframe alignment has been lost, or if the last multiframe has been received with crc error(s). si1 flags a crc error in last sub-multiframe 1, si2 flags a crc error in last sub-multiframe 2. 1 ... if at multiframe synchronous state last assigned sub-multiframe has been received without a crc error. both flags will be actualized with beginning of every received crc multiframe. if automatic transmission of sub-multiframe status is enabled by setting bit xsp.axs, above status information will be inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time-slot 0 transparent modes are both disabled): si1 ? s i -bit of frame 13, si2 ? s i -bit of frame 15. 70 rsw rsi 1 rra ryo ry1 ry2 ry3 ry4 (4e) 70 rsp si1 si2 rsif rs13 rs15 (4f)
peb 2254 operational description e1 semiconductor group 125 11.96 rsif receive spare bit for international use (fas word) first bit in fas-word. used only in doubleframe format, otherwise fixed to 1. rs13 receive spare bit (frame 13, crc multiframe) first bit in service word of frame 13. significant only in crc- multiframe format, otherwise fixed to 0. this bit is updated with beginning of every received crc multiframe. rs15 receive spare bit (frame 15, crc multiframe) first bit in service word of frame 15. significant only in crc- multiframe format, otherwise fixed to 0. this bit is updated with beginning of every received crc multiframe. framing error counter (read) fe15fe0 framing errors this 16-bit counter will be incremented when a fas word has been received with an error. framing errors will not be counted during asynchronous state. during alarm simulation, the counter is incremented every 250 m s up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dfec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe8 (51)
peb 2254 operational description e1 semiconductor group 126 11.96 code violation counter (read) cv15cv0 code violations no function if nrz code has been enabled. if the hdb3 or the cmi code is selected, the 16-bit counter will be incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit fmr0.extd. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcvc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv8 (53)
peb 2254 operational description e1 semiconductor group 127 11.96 crc error counter 1 (read) cr15cr0 crc errors no function if doubleframe format is selected. in crc-multiframe mode, the 16-bit counter will be incremented when a crc-submultiframe has been received with a crc error. crc errors will not be counted during asynchronous state. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec1 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec1 will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec1l cr7 cr0 (54) 70 cec1h cr15 cr8 (55)
peb 2254 operational description e1 semiconductor group 128 11.96 e bit error counter (read) eb15eb0 e-bit errors if doubleframe format is selected, febeh/l has no function. if crc- multiframe mode is enabled, febeh/l works as submultiframe error indication counter (16 bits) which counts zeros in si-bit position of frame 13 and 15 of every received crc multiframe. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.debc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl eb7 eb0 (56) 70 ebch eb15 eb8 (57)
peb 2254 operational description e1 semiconductor group 129 11.96 crc error counter 2 (read) cc15cc0 crc error counter (reported from te via sa6 -bit) if doubleframe format is selected, cec2h/l has no function. if crc- multiframe mode is enabled, cec2h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0001 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa61, sa62, sa63, sa64 = 0001 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented once per multiframe up to its saturation. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec2 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec2 will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec2l cc7 cc0 (58) 70 cec2h cc15 cc8 (59)
peb 2254 operational description e1 semiconductor group 130 11.96 crc error counter 3 (read) ce15ce0 crc error counter (detected at t ref. point via sa6 -bit) if doubleframe format is selected, cec3h/l has no function. if crc- multiframe mode is enabled, cec3h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0010 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa61, sa62, sa63, sa64 = 0010 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented once per multiframe up to its saturation. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec3 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec3 will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec3l ce7 ce0 (5a) 70 cec3h ce15 ce8 (5b)
peb 2254 operational description e1 semiconductor group 131 11.96 receive sa4-bit register (read) rs47rs40 receive sa4-bit data (y-bits) this register contains the information of the eight sa4 bits of the previously received crc multiframe (bit-slot 4 of every service word). rs40 is received in frame 1, rs47 in frame 15. this register will be updated with every multiframe begin interrupt isr0.rmb. valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). receive sa5-bit register (read) rs57rs50 receive sa5-bit data (y-bits) this register contains the information of the eight sa5 bits of the previously received crc multiframe (bit-slot 5 of every service word). rs50 is received in frame 1, rs57 in frame 15. this register will be updated with every multiframe begin interrupt isr0.rmb. valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). receive sa6-bit register (read) rs67rs60 receive sa6-bit data (y-bits) this register contains the information of the eight sa6 bits of the previously received crc multiframe (bit-slot 6 of every service word). rs60 is received in frame 1, rs67 in frame 15. this register will be updated with every multiframe begin interrupt isr0.rmb. valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). 70 rsa4 rs47 rs40 (5c) 70 rsa5 rs57 rs50 (5d) 70 rsa6 rs67 rs60 (5e)
peb 2254 operational description e1 semiconductor group 132 11.96 receive sa7-bit register (read) rs77rs70 receive sa7-bit data (y-bits) this register contains the information of the eight sa7 bits of the previously received crc multiframe (bit-slot 7 of every service word). rs70 is received in frame 1, rs77 in frame 15. this register will be updated with every multiframe begin interrupt isr0.rmb. valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). receive sa8-bit register (read) rs87rs80 receive sa8-bit data (y-bits) this register contains the information of the eight sa8 bits of the previously received crc multiframe (bit-slot 8 of every service word). rs80 is received in frame 1, rs87 in frame 15. this register will be updated with every multiframe begin interrupt isr0.rmb. valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). receive sa6-bit status (read) four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the falc54 will detect the following fixed sa6-bit combinations: sa61,sa62,sa63,sa64=1000; 1010; 1100; 1110; 1111. all other possible 4 bit combinations are grouped to status x. 70 rsa7 rs77 rs70 (5f) 70 rsa8 rs87 rs80 (60) 70 rsa6s s_x s_f s_e s_c s_a s_8 (61)
peb 2254 operational description e1 semiconductor group 133 11.96 a valid sa6-bit combination must occur three times in a row. the corresponding status bit in this register will be set. even if the detected status will be active for a short time the status bit remains active until this register is read. reading the register will reset all pending status information. with any change of state of the sa6-bit combinations an interrupt status isr0.sa6sc will be generated. during the basicframe asynchronous state updating of this register and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synch. state (frs0.lmfa=0). in asynchr. detection mode updating is independent to the multiframe synchronous state. s_x receive sa6-bit status_x if none of the fixed sa6-bit combinations are detected this bit will be set. s_f receive sa6-bit status: 1111 receive sa6-bit status 1111 is detected for three times in a row in the sa6-bit positions. s_e receive sa6-bit status: 1110 receive sa6-bit status 1110 is detected for three times in a row in the sa6-bit positions. s_c receive sa6-bit status: 1100 receive sa6-bit status 1100 is detected for three times in a row in the sa6-bit positions. s_a receive sa6-bit status: 1010 receive sa6-bit status 1010 is detected for three times in a row in the sa6-bit positions. s_8 receive sa6-bit status: 1000 receive sa6-bit status 1000 is detected for three times in a row in the sa6-bit positions.
peb 2254 operational description e1 semiconductor group 134 11.96 signaling status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres C or when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable data can be written to the xfifo. xrep transmission repeat status indication of cmdr.xrep. rli receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec command executing 0 no command is currently executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 5 sclkx clock cycles if fmr1.imod=0 and 10 sclkx cycles if fmr1.imod is set. 70 sis xdov xfw xrep rli cec (64)
peb 2254 operational description e1 semiconductor group 135 11.96 receive signaling status register (read) rsis relates to the last received hdlc frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame determines whether a valid frame has been received. 1 valid 0 invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or C a frame which is too short taking into account the operation mode selected via mode (mds2-0) and the selection of receive crc on/off (ccr3.rcrc) as follows: ? mds2-0 = 011 (16 bit address), rcrc = 0 : 4 bytes; rcrc = 1 : 3-4 bytes ? mds2-0 = 010 (8 bit address), rcrc = 0 : 3 bytes; rcrc = 1 : 2-3 bytes note: shorter frames are not reported. rdo receive data overflow a rfifo data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check 0 crc check failed; received frame contains errors. 1 crc check o.k.; received frame is error-free. rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. 70 rsis vfr rdo crc16 rab ha1 ha0 la (65)
peb 2254 operational description e1 semiconductor group 136 11.96 ha1, ha0 high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the falc54 compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 00 rah2 has been recognized 01 broadcast address has been recognized 10 rah1 has been recognized c/r = 0 (bit 1) 11 rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by 10 or 11. la low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ral2 has been recognized 1 ral1 has been recognized receive byte count low (read) together with rbch (bits rbc11 - rbc8), indicates the length of a received frame (14095 bytes). bits rbc4-0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. 70 rbcl rbc7 rbc0 (66)
peb 2254 operational description e1 semiconductor group 137 11.96 received byte count high (read) value after reset: 000 xxxxx ov counter overflow more than 4095 bytes received. rbc11 C rbc8receive byte count (most significant bits) together with rbcl (bits rbc7rbc0) indicate the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit ipc.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc4C0. additional information is available in the rsis register. 70 rbch ov rbc11 rbc8 (67) 70 isr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (68)
peb 2254 operational description e1 semiconductor group 138 11.96 rfs receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of ? ral1 ? rsis - bits 3-1 are valid and can be read by the cpu. t8ms receive time out 8 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt will be set to indicate that no multiframing could be found within a time window of 8 msec. in multiframe synchronous state this interrupt will be not generated. refer also to floating multiframe alignment window. rmb receive multiframe begin this bit is set with the beginning of a received crc multiframe related to the internal receive line timing. in crc multiframe format fmr2.rfs1 = 1 or in doubleframe format fmr2.rfs1/0 = 01 this interrupt occurs every 2 msec. if fmr2.rfs1/0 = 00 this interrupt will be generated every doubleframe (512 bits). casc received cas information changed this bit is set with the updating of a received cas multiframe information in the registers rs1-16. if the last received cas information changed from the previous received updating is started. this interrupt will only occur in the ts0 and ts16 synchronous state. the registers rs1-16 should be read within the next 2 ms otherwise the contents may be lost. crc4 receive crc4 error 0... no crc4 error occurs. 1... the crc4 check of the last received submultiframe failed. sa6s c receive sa6-bit status changed with every change of state of the received sa6-bit combinations this interrupt will be set.
peb 2254 operational description e1 semiconductor group 139 11.96 rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. if bit ipc.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rdo receive data overflow this interrupt status indicates that the cpu does not respond quickly enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent this bit is set if the last bit of the current frame is completely sent out and xfifo is empty. xdu transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. 70 isr1 rdo alls xdu xmb xlsc xpr (69)
peb 2254 operational description e1 semiconductor group 140 11.96 xmb transmit multiframe begin this bit is set every 2 ms with the beginning of a transmitted multiframe related to the internal transmitter timing. just before setting this bit registers xs1-16 are copied in the transmit shift registers. the registers xs1-16 are empty and has to be updated otherwise the contents will be retransmitted. xlsc transmit line status change xlsc is set to one with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit ipc.vis is set to 1, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached doubleframe synchronization. set when bit fsr0.lfa is reset. it is set also after alarm simulation is finished and the receiver is still synchron. lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it will be set during alarm simulation. 70 isr2 far lfa mfar t400ms ais los rar ra (6a)
peb 2254 operational description e1 semiconductor group 141 11.96 mfar multiframe alignment recovery set when the framer has found two crc-multiframes at an interval of n x 2 ms (n = 1, 2, 3, ) without a framing error. at the same time bit frs0.lmfa is reset. it is set also after alarm simulation is finished and the receiver is still synchron. only active if crc-multiframe format is selected. t400ms receive time out 400 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt will be set to indicate that no multiframing could be found within a time window of 400 msec after basic framing has been achieved. in multiframe synchronous state this interrupt will not be generated. ais alarm indication signal this bit is set when an alarm indication signal is detected and bit frs0.ais is set. it will be set during alarm simulation. if ipc.sci is set high this interrupt status bit will be set with every change of state of frs0.ais. los loss of signal this bit is set when a loss of signal alarm is detected in the received bitstream and frs0.los is set. it will be set during alarm simulation. if ipc.sci is set high this interrupt status bit will be set with every change of state of frs0.los. rar remote alarm recovery set if a remote alarm in ts0 is cleared and bit frs0.ra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm set if a remote alarm in ts0 is detected and bit frs0.ra is set. it will be set during alarm simulation.
peb 2254 operational description e1 semiconductor group 142 11.96 interrupt status register 3 (read) all bits are reset when isr3 is read. if bit ipc.vis is set to 1, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es errored second this bit is set if at least one enabled interrupt source via imr4 is set during the time interval of one second. interrupt sources of imr4 register: lfa = loss of frame alignment detected (frs0.lfa) fer = framing error received cer= crc error received ais = alarm indication signal (frs0.ais) los = loss of signal (frs0.los) cve = code violation detected slip= receive slip positive/negative detected ebe = e- bit error detected (rsp.si1/si2 =0) sec second the internal one second timer has expired. the timer is derived from the internal 16 mhz clock. lmfa16 loss of multiframe alignment ts 16 multiframe alignment of timeslot 16 has been lost if two consecutive multiframe pattern are not detected or if in 16 consecutive timeslot 16 all bits are reset. if register ipc.sci is high this interrupt status bit will be set with every change of state of frs1.ts16lfa. ais16 alarm indication signal ts 16 status change the alarm indication signal ais in timeslot 16 for the 64 kbit/s channel associated signaling is detected or cleared. a change in bit frs1.ts16ais will set this interrupt. (this bit is set if the incoming ts 16 signal contains less than 4 zeros in each of two consecutive ts16- multiframe periods.) 70 isr3 es sec lmfa16 ais16 ra16 api sln slp (6b)
peb 2254 operational description e1 semiconductor group 143 11.96 ra16 remote alarm ts 16 status change a change in the remote alarm bit in cas multiframe alignment word is detected. api auxiliary pattern indication this bit is set if the auxiliary pattern is detected in the received bitstream and bit frs0.auxp is set. if register ipc.sci is high this interrupt status bit will be set with every change of state of frs0.auxp. sln slip negative the frequency of the receive route clock is greater than the frequency of sclkr/4. a frame will be skipped. it will be set during alarm simulation. slp slip positive the frequency of the receive route clock is less than the frequency of sclkr/4. a frame will be repeated. it will be set during alarm simulation. global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts (isr3 ... isr0). version status register (read) vn3 C vn0 version number of chip 0version 1.1 - 1.2 1version 1.3 70 gis isr3 isr2 isr1 isr0 (6e) 70 vstr vn3 vn0 (6f)
peb 2254 operational description e1 semiconductor group 144 11.96 receive cas register (read) value after reset: not defined receive cas register 1-16 each register except rs1 contains the received cas bits for two timeslots. the received cas multiframe will be compared with the previously received one. if the contents changed a cas multiframe changed interrupt (isr0.casc) is generated and informs the user that a new multiframe has to be read within the next 2 ms. if requests for reading the rs1-16 register are ignored, the received data may be lost. rs1 contains frame 0 of the cas multiframe. msb is received first. 70 rs1 0 0 0 0 x y x x (70) rs2 a1 b1 c1 d1 a16 b16 c16 d16 (71) rs3 a2 b2 c2 d2 a17 b17 c17 d17 (72) rs4 a3 b3 c3 d3 a18 b18 c18 d18 (73) rs5 a4 b4 c4 d4 a19 b19 c19 d19 (74) rs6 a5 b5 c5 d5 a20 b20 c20 d20 (75) rs7 a6 b6 c6 d6 a21 b21 c21 d21 (76) rs8 a7 b7 c7 d7 a22 b22 c22 d22 (77) rs9 a8 b8 c8 d8 a23 b23 c23 d23 (78) rs10 a9 b9 c9 d9 a24 b24 c24 d24 (79) rs11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) rs12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) rs13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) rs14 a13 b13 c13 d13 a28 b28 c28 d28 (7d) rs15 a14 b14 c14 d14 a29 b29 c29 d29 (7e) rs16 a15 b15 c15 d15 a30 b30 c30 d30 (7f)
semiconductor group 145 11.96 framing and line interface component falc54 peb 2254 cmos p-mqpf-80-1 type version ordering code package peb 2254-h v1.3 q67103-h6813 p-mqfp-80 (smd) falc54 in pcm 24 mode 4 general features t1 line interface ? analog receive and transmit circuitry ? data and clock recovery using an integrated digital phase locked loop ? maximum line attenuation up to 18 db (itu-t i.431) adaptively controlled receiver threshold ? low transmitter output impedance for a high return loss with reasonable protection resistors ? tri-state function of the analog transmit line outputs ? programmable transmit pulse shape using a minimum number of external components ? jitter specifications of itu-t i.431, g.703 and at&t tr 62411 met ? wander and jitter attenuation/compensation clock smoothing ? dual rail or single rail digital inputs and outputs ? unipolar nrz for interfacing fibre optical transmission routes ? selectable line codes (b8zs, ami with zcs) ? loss of signal indication with programmable thresholds according to itu-t g.775 and ansi t1. 403 ? clock generator for jitter free system clocks and transmit clock using an digital phase locked loop ? transmit line monitor ? local loop and remote loop for diagnostic purposes ? only one type of transformer (ratio 1: ? 2) for cept 75/120 w and t1 100 w
semiconductor group 146 11.96 peb 2254 general features t1 frame aligner ? frame alignment/synthesis for 1544 kbit/s according to itu-t g.704 ? meets newest itu-t rec's, ansi t1 and at&t technical references ? programmable formats for pcm 24: 4-frame multiframe (f4), 12-frame multiframe (f12, d3/4), extended superframe (esf), remote switch mode (f72, slc96) ? selectable conditions for loss of frame alignment ? error checking via crc6 procedures according to itu-t g. 706 ? performance monitoring 16 bit counter for crc-, framing errors, code violations, errored blocks ? insertion and extraction of alarms (ais, remote (yellow) alarm, ) ? idle code insertion for selectable channels ? 8192 khz system clock frequency different for receiver and transmitter ? selectable 2048/4096 kbit/s backplane interface with programmable receive/transmit shifts programmable tri-state function of 4096 kbit/s output via rdo ? two-frame elastic store for receive route clock wander and jitter compensation; controlled slip capability and slip indication ? one frame elastic store for transmit route clock wander and jitter compensation ? support for different data link schemes ? clear channel capabilities ? flexible transparent modes ? in band loop code detection and generation according to tr 62411 ? channel loop back, line loop back or payload loop back capabilities (at&t tr 54016) signaling controller ? hdlc controller bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions, programmable preamble ? dl-channel protocol for esf format according to t1.403-1989 ansi specification or according to at&t tr54016. ? robbed bit signaling with last look capability ? dl-access for f72 (slc96) format ? transparent mode ? fifo buffers (64 bytes deep) for efficient transfer of data packets. ? time-slot assignment any combination of time slots selectable for data transfer independent of signaling mode. useful for fractional t1 applications.
peb 2254 general features t1 semiconductor group 147 11.96 mp interface ? 8/16 bit microprocessor bus interface (intel or motorola type) ? all registers directly accessible (byte or word access) ? extended interrupt capabilities general ? boundary scan standard ieee 1149.1 ? advanced cmos technology ? p-mqfp-80 package the falcs power consumption is mainly determined by the line length and type of the cable and typical 450 mw.
semiconductor group 148 11.96 peb 2254 general features t1 4.1 pin configuration of falc (top view) figure 33 p-mqfp-80-1
peb 2254 general features t1 semiconductor group 149 11.96 note: all unused input pins including pin 80 have to be connected to a defined level 4.2 pin definitions and function pin no. symbol input (i) output (o) function 42 48 a0 a6 i address bus these inputs interface with seven bits of the systems address bus to select one of the internal registers for read or write. 4138 3528 2522 d0 d3 d4 d11 d12 d15 i/o data bus bi-directional three-state data lines which interface with the systems data bus. their configuration is controlled by the level of pin dbw: C 8-bit mode (dbw = 0): d0 d7 are active. d8 d15 are in high impedance and have to be connected to v dd or v ss . C 16-bit mode (dbw = 1): d0 d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe/ ble and the selected bus interface mode (via pin im). the unused half is in high impedance. for detailed information, refer to chapter 4.6 . 49 ale i address latch enable a high on this line indicates an address on the external address/data bus. the address information provided on lines a0 a6 is internally latched with the falling edge of ale. this function allows the falc54 to be directly connected to a multiplexed address/data bus. in this case, pins a0 a6 must be externally connected to the data bus pins.in case of demultiplexed mode this pin has to be connected directly to ground or vdd. for detailed information, refer to chapter 4.6 .
semiconductor group 150 11.96 peb 2254 general features t1 pin definitions and function (contd) pin no. symbol input (i) output (o) function 50 rd/ ds i read enable (siemens/intel bus mode) this signal indicates a read operation. when the falc54 is selected via cs the rd signal enables the bus drivers to output data from an internal register addressed via a0 a6 on to data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 4.6 . data strobe (motorola bus mode) this pin serves as input to control read/write operations. 51 wr/r wi write enable (siemens/intel bus mode) this signal indicates a write operation. when cs is active the falc54 loads an internal register with data provided via the data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 4.6 . read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 52 cs i chip select a low signal selects the falc54 for read/write operations. 54 res i reset a high signal on this pin forces the falc54 into reset state. during reset the falc54 needs active clocks on pins sclkr, sclkx, xtal1 and xtal3. during reset C all uni-directional output stages are in high- impedance state, except pins clk16m, clk12m, clk8m, clkx, fsc, xclk and rclk C all bi-directional output stages (data bus) are in high-impedance state if signal rd is high, output xtal2/4 is in high-impedance if input xtal1/3 is high.
peb 2254 general features t1 semiconductor group 151 11.96 53 bhe/ ble i bus high enable (siemens/intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d8 d15). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 4.6 for detailed information. bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 d7). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 4.6 for detailed information. 11 dbw i data bus width (bus interface mode) a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe/ ble. 56 int o/od interrupt request int serves as general interrupt request which may include all interrupt sources. these interrupt sources can be masked via registers imr0 4. interrupt status is reported via registers gis (global interrupt status) and isr0 3. output characteristics (push-pull active low/high, open drain) are determined by programming the ipc register. 8im i interface mode the level at this pin defines the bus interface mode: a low signal on this input selects the intel interface mode. a high signal on this input selects the motorola interface mode. 1 v ddr i positive power supply for the analog receiver pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 152 11.96 peb 2254 general features t1 2 rl1 rdip roid i i i line receiver 1 analog input from the external transformer. selected if lim1.drs = 0. receive data input positive digital input for received dual rail pcm(+) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive optical interface data unipolar data received from fibre optical interface with 1544 kbit/s. latching of data is done with the falling edge of rclki. input sense is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. 3 refr o reference resistance of 12 k w 1 % connected to v ss pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features t1 semiconductor group 153 11.96 4 rl2 rdin rclki i i i line receiver 2 analog input from the external transformer. selected if lim1.drs = 0. receive data input negative input for received dual rail pcm(-) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive clock input receive clock input for the optical interface if lim1.drs = 1 and fmr0.rc1/0 = 00. clock frequency: 1544 khz 5 v ssr i power ground supply for analog receiver 6 7 xtal2 xtal1 o i crystal connection 16.384 mhz when an external clock is used, normally if the bit lim0.mas is set, the falc54 functions as a master. 9 10 xtal4 xtal3 o i crystal connection 12.352 mhz a crystal has to be connected to these pins to generate the transmit clock. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 154 11.96 peb 2254 general features t1 13 xl2 xdon o o transmit line 2 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output negative this digital output for transmitted dual rail pcm(-) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. 14 v ssx i ground for analog transmitter pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features t1 semiconductor group 155 11.96 15 xl1 xdop xoid o o o transmit line 1 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output positive this digital output for transmitted dual rail pcm(+) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit optical interface data unipolar data sent to fibre optical interface with 1544 kbit/s which will be clocked off on the positive transitions of xclk. clocking off data in nrz code is done with 100 % duty cycle. output sense is selected by bit lim0.xdos (after reset: data are sent active high). the single rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 0. after reset this pin is in a high impedance state until register lim1.drs is set to one. 17 xl1m i transmit line 1 monitor analog input from the external transmit transformer (xl1). this pin must be connected otherwise the xl1 pin could be set in a high impedance state. if digital inputs are selected (lim1.drs = 1) this input has to be switched to v ssx . pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 156 11.96 peb 2254 general features t1 12 xl2m i transmit line 2 monitor analog input from the external transmit transformer (xl2). this pin must be connected otherwise the xl2 pin could be set in a high impedance state. if digital inputs are selected via lim1.drs = 1 this input has to be switched to v ssx . 16 vddx i positive power supply for analog transmitter 79 xclk fsc o o transmit clock transmit clock frequency: 1544 khz. derived from the xtal3 or rclk or internally generated. if lim1.efsc is set high an 8-khz frame synchronization pulse is output via this pin. the synchronization pulse is active high for one 2 mhz cycle (pulse width = 488 ns) and is derived from the clock supplied by pin xtal1. 80 n.c. not connected. for further application this pin should be connected to v ss . 66 fsc o 8-khz frame synchronization pulse is active low for one 2 mhz cycle (pulse width = 488 ns) and is derived from the clock supplied by pin xtal1. 75 clk16m o system clock 16.384 mhz 76 clk12m o system clock 12.352 mhz only if a crystal or an oscillator is connected to xtal3/4. 77 clk8m o system clock 8.192 mhz the frequency is derived from the clock supplied by pin xtal1. 78 clkx o system clock output output frequencies are: 2.048 mhz or 4.096 mhz inverted or non-inverted. the frequency and sense on this pin is selectable via lim0.scl1/0 and is derived from the clock supplied by pin xtal1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features t1 semiconductor group 157 11.96 60 sync i clock synchronization if a clock is detected at the sync pin the falc54 synchronizes to this clock 1.544 mhz or 2.048 mhz (if lim1.dcoc = 1). this pin has to be connected to v ss if no clock is supplied. 72 rclk o receive clock extracted from the incoming data pulses clock frequency: 1544 khz if lim0.elos is set, the rclk is set high in case of loss of signal (frs0.los=1). 57 rdo o receive data out received data which is sent to the system internal highway with 4096 kbit/s or 2048 kbit/s (bit fmr1.imod). in 4096 kbit/s mode data is shifted out in that channel phase which is selected by register rc0.sics.the other channel phase is set in tri-state. clocking off data is done with the falling edge of sclkr. the delay between the beginning of time-slot 0 and the initial edge of sclkr (after sypr goes active) is determined by the values of receive time-slot offset rc1.rto5 0, receive clock-slot offset rc0.rco2 0 and rc0.rcos. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 158 11.96 peb 2254 general features t1 71 rfsp/ freezs o receive frame synchronous pulse/ freeze signaling if xc0.sfrz is set to 0 the receive frame synchronous pulse (pulse width = 648 ns) is output on this pin. pulse frequency: 8 khz. if xc0.sfrz is set high the freeze signaling status is indicated. synchronization status signal which informs the signaling processor that current signaling should be frozen. it goes active if C one or more framing bit errors are found in a superframe, C loss of receiver synchronization, or C a receive slip is detected. it is cleared after an error-free superframe. during alarm simulation, this signal goes active during simulation steps 2 and 6. 70 dlr o data link bit receive this output provides a 4 khz signal which marks the dl-bit position within the data stream on rdo. it can be used as receive strobe signal for external data link controllers. in 4096 kbit/s mode dlr is active only during the channel phase which is selected by rc0.sics. 68 xmfb o transmit multiframe begin the function depends on programming bit xc0.mfbs: mfbs = 1: xmfb marks the beginning of every transmitted multiframe (xdi). mfbs = 0: marks the beginning of every transmitted superframe. additional pulses every 12 frames are provided when using esf or f72 format. xmfb is always active high for one 2048 kbit/s period. in 4096 kbit/s mode xmfb is active during the first two bits of the multiframe. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features t1 semiconductor group 159 11.96 59 xsigm o transmit signaling marke r C marks the transmit time-slots which are defined by register ttr1-4 of every frame transmitted via port xdi. C when using the cas-br signaling scheme (bit fmr1.sigm = 1), the robbed bit of each channel every six frames is marked, if it is enabled via register xc0.brm = 1. in 4096 kbit/s mode xsigm is active only during the channel phase which is selected by rc0.sics. 65 sypr i synchronous pulse receive defines the beginning of time-slot 0 at system highway port rdo in conjunction with the values of registers rc0.rco, rc0.rcos and rc1.rto. sampling is done with the falling edge of the sclkr clock . pulse cycle: integer multiple of 125 m s. 64 sypx i synchronous pulse transmit defines the beginning of time-slot 0 at system highway port xdi in conjunction with the values of registers xc0.xco, xc1.xto and xc1.xcos. sampling is done with the falling edge of the sclkx clock. pulse cycle: integer multiple of 125 m s. 63 sclkr i system clock receive working clock for the falc54 with a frequency of 8192 khz. 62 sclkx i system clock transmit working clock for the falc54 with a frequency of 8192 khz. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 160 11.96 peb 2254 general features t1 55 xdi i transmit data in transmit data received from the system internal highway with 4096 kbit/s or 2048 kbit/s (bit fmr1.imod). latching of data is done with negative transitions of sclkx. in 4096 kbit/s mode data is sampled in the first channel phase if rc0.sics is low. if rc0.sics is high data is sampled in the second channel phase. the delay between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is determined by the values of transmit time-slot offset xc1.xto5 0, transmit clock-slot offset xc0.xco2 0 and xc1.xcos. 69 dlx o data link bit transmit this output provides a 4 khz signal which marks the dl-bit position within the data stream on xdi. it can be used as transmit strobe signal for external data link controllers. in 4096 kbit/s mode dlx is active only during the channel phase which is selected by rc0.sics. 58 rsigm o receive signaling marker C marks the time-slots which are defined by register rtr1-4 of every received frame at port rdo. C when using the cas-br signaling scheme (bit fmr1.sigm = 1), the robbed bit of each channel every six frames is marked, if it is enabled via register xc0.brm = 1. in 4096 kbit/s mode rsigm is active high only during the channel phase which is selected by rc0.sics. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 2254 general features t1 semiconductor group 161 11.96 67 rmfb o receive multiframe begin the function depends on programming bit xc0.mfbs: mfbs = 1: rmfb marks the beginning of every received multiframe (rdo). mfbs = 0: marks the beginning of every received superframe. additional pulses every 12 frames are provided when using esf or f72 format. rmfb is always active high for one 2048 kbit/s period. in 4096 kbit/s mode rmfb is active during the first two bits of the multiframe. 61 xmfs i external transmit multiframe synchronization this port operates as an input for external transmit multiframe synchronization which defines frame 1 of the multiframe on xdi. minimum pulse length is 244 ns. latching is done equivalent to latching data via xdi. the signal has to be issued during frame 1 and has to be reset at least one bit before begin of frame 2. recommended: xmfs begins with the first bit of time-slot 0, frame 1 of xdi. note : a new multiframe position has been settled at least one multiframe after pulse xmfs has been supplied. 27, 37, 74 v ss i power ground supply for digital subcircuits (0 v) for correct operation, all three pins have to be connected to ground. 26, 36, 73 v dd i positive power supply for the digital subcircuits (5 v) for correct operation, all three pins have to be connected to positive power supply. 18 tdi i test data input for boundary scan acc. to ieee std. 1149.1 21 tdo o test data output for boundary scan 19 tms i test mode select for boundary scan 20 tck i test clock for boundary scan pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 162 11.96 peb 2254 general features t1 4.3 logic symbol figure 34 falc54 logic symbol
peb 2254 general features t1 semiconductor group 163 11.96 4.4 functional block diagram figure 35 functional block diagram peb 2254
semiconductor group 164 11.96 peb 2254 general features t1 4.5 system integration the figures below show a multiple link application and a nt application. figure 36 multiple link application
peb 2254 general features t1 semiconductor group 165 11.96 figure 37 nt - application 4.6 microprocessor interface the communication between the cpu and the falc54 is done via a set of directly accessible registers. the interface may be configured as siemens/intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers data to/from the falc54 (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe/ ble as shown in table 11 and 12 . in table 13 is shown how the ale (address latch enable) line is used to control the bus structure and interface type. the switching of ale allows the falc54 to be directly connected to a multiplexed address/data bus.
semiconductor group 166 11.96 peb 2254 general features t1 mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. table 11 data bus access (16-bit intel mode) table 12 data bus access (16-bit motorola mode) table 13 selectable bus and microprocessor interface configuration bhe a0 register access falc54 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d8 C d15 1 0 register byte access (even addresses) d0 C d7 1 1 no transfer performed none ble a0 register access falc54 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d0 C d7 1 0 register byte access (even addresses) d8 C d15 1 1 no transfer performed none ale im microprocessor interface bus structure gnd/vdd 1 motorola demultiplexed gnd/vdd 0 intel demultiplexed switching 0 intel multiplexed
peb 2254 general features t1 semiconductor group 167 11.96 the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: siemens/intel (adr. n + 1) (adr. n) motorola (adr. n) (adr. n + 1) -- n: even address complete information concerning register functions is provided in C detailed register description. fifo structure in transmit and receive direction of the signaling controller 64-byte deep fifos are provided for the intermediate storage of data between the system internal highway and the cpu interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cpu at any time. in case 16-bit data bus width is selected by fixing pin dbw to logical 1 word access to the fifos is enabled. data output to bus lines d0-d15 as a function of the selected interface mode is shown in figure 38 and 39 . of course, byte access is also allowed.the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 2 bytes. data lines d15 d8 d7 d0
semiconductor group 168 11.96 peb 2254 general features t1 figure 38 fifo word access (intel mode)
peb 2254 general features t1 semiconductor group 169 11.96 figure 39 fifo word access (motorola mode)
semiconductor group 170 11.96 peb 2254 general features t1 interrupt interface special events in the falc54 are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; ipc register), which requests the cpu to read status information from the falc, or to transfer data from/to falc. since only one int request output is provided, the cause of an interrupt must be determined by the cpu by reading the falcs interrupt status registers (gis, isr0, isr1, isr2, isr3) that means the interrupt at pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr0-3 are from type clear on read. the structure of the interrupt status registers is shown in figure 40 . figure 40 falc54 interrupt status registers each interrupt indication of registers isr0, isr1, isr2 and isr3 can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0, imr1, imr2, imr3. if the interrupt status bits are masked they neither generate an interrupt at int nor are they visible in isr0-3. gis, the non-maskable global interrupt status register, serves as pointer to pending channel related interrupts. after the falc54 has requested an interrupt by activating its int pin, the cpu should first read the global interrupt status register gis to identify the requesting interrupt source register. after reading the assigned interrupt status registers isr0- isr3, the pointer in register gis is cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (gis is reset), pin int goes inactive. updating of interrupt status registers isr03 and gis is only prohibited during read access.
peb 2254 general features t1 semiconductor group 171 11.96 masked interrupts visible in status registers the global interrupt status register (gis) indicates those interrupt status registers with active interrupt indications (gis.isr0-3). an additional mode can be selected via bit ipc.vis. in this mode, masked interrupt status bits neither generate an interrupt at pin int nor are they visible in gis, but are displayed in the respective interrupt status register(s) isr0..3 . this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. notes: ? in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. ? all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no hierarchical polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts.
peb 2254 general functions and device architecture t1 semiconductor group 172 11.96 5 general functions and device architecture t1 5.1 functional description t1 5.1.1 receive path figure 41 receive clock system receive line interface for data input, four different data types are supported: ? ternary coded signals received at multifunction ports rl1 and rl2 from a 6 db ternary interface. the ternary interface is selected if lim1.drs is reset. ? ternary coded signals received at multifunction ports rl1 and rl2 from a 18 db ternary interface. the ternary interface is selected if lim1.drs is reset. ? digital dual rail signals received at ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. ? unipolar data at port roid received from a fibre optical interface. the optical interface is selected if lim1.drs is set fmr0.rc1 is reset.
peb 2254 general functions and device architecture t1 semiconductor group 173 11.96 receive equalizer the itu-t i.431 recommendation requires a minimum loop length of 18 db for t1 applications. the falc54 meets this requirement by the integrated receive equalizer. enabling and disabling the receive equalizer can be performed via a control bit. receive clock and data recovery the analog received signal at port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal at port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rclk from the received data stream at ports rl1/2, rdip/rdin or roid and converts the data stream into a single rail, unipolar bit stream. the clock and data recovery works with the frequency supplied by xtal3/4. normally the clock that is output via pin rclk is the recovered clock from the signal provided by rl1/2 or rdip/n and has a duty cycle close to 50 %. the free run frequency is defined by xtal3/4 devided by 8 in periods with no signal. receive line coding a selection between b8zs or simple ami (zcs) coding is employed for the ternary or the dual rail interface. in this case, all code violations that do not correspond to zero substitution rules will be detected. the detected errors increment the code violation counter (16 bits length). in the optical interface mode the nrz coding is automatically performed.in this case data will be latched with the falling edge of pin rclki. when using the optical interface with nrz coding, the decoder is by-passed and no code violations will be detected. additionally, the receive line interface comprises the alarm detection for alarm indication signal ais (blue alarm) and the loss of signal los (red alarm). the signal at the ternary interface is received at both ends of a transformer. figure 42 receiver configuration
peb 2254 general functions and device architecture t1 semiconductor group 174 11.96 table 14 recommended receiver configuration values jitter free system clocks (16 mhz / 8 mhz / 4 mhz / 2 mhz and 8 khz) are generated by the internal pll circuit dco1. the dco1 can work in two different modes: ? slave mode in slave mode (lim0.mas = 0), the dco1 will be synchronized on the recovered route clock. in case of los the dco1 switches automatically to master mode. ? master mode in master mode (lim0.mas = 1), the oscillator is in free running mode if pin sync is connected to vss. if there is a frequency of 1.544 mhz (lim1.dcoc = 0) or 2.048 mhz (lim1.dcoc = 1) at the sync input the dco1 is then synchronized to this input. loss of signal detection there are different definitions for detecting loss of signal alarms (los) in the itu-t g.775 and at&t tr 54016. the falc54 covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register ipc.sci. ? detection: an alarm will be generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. no pulse in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for no pulse in the analog receive interface (lim1.drs=0). the receive signal level q is programmable via three control bits lim1.ril2-0 in a range of about 1400 to 200 mv differential voltage between pins rl1/2. the number n can be set via a 8 bit register pcd. the contents of the pcd register will be multiplied by 16, which results in the number of pulse periods, or better, the time which has to suspend until the alarm has to be detected. the range results therefore from 16 to 4096 pulse periods. ? recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2-0) of the nominal pulse. the value in the 8 bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. parameter characteristic impedance 100 w ds1 (6 db) t1 (18 db) r 1 ( 2.5 %) [ w ]00 t 2 : t 1 1 : ? 21 : ? 2 r 2 ( 2.5 %) [ w ] 200 200
peb 2254 general functions and device architecture t1 semiconductor group 175 11.96 jitter attenuator together with a pll and a tunable crystal attenuation of received input jitter is done in the clock- and data-recovery and either in the received elastic buffer (2 frames) or in the jitter attenuator jatt block of figure 3. the attenuator consists of a 288 bit fifo. the fifo is placed in the transmitter and will be active if bit lim1.jatt=1 , remote loop active. the jitter attenuator meets the jitter transfer requirements of the pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and rec. i.431 and g.703 (refer to figure 43 ). figure 43 jitter attenuation performance
peb 2254 general functions and device architecture t1 semiconductor group 176 11.96 jitter tolerance the falc54 receivers tolerance to input jitter complies to itu and bellcore requirements and t1 application. figure 44 shows the curves of different input jitter specifications stated above as well as the falc54 performance. figure 44 jitter tolerance output jitter in the absence of any input jitter the falc54 generates the output jitter, which is specified in table below. specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff pub 62411 10 hz 8 khz < 0.02 8 khz 40 khz < 0.025 10 hz 40 khz < 0.025 broadband < 0.05
peb 2254 general functions and device architecture t1 semiconductor group 177 11.96 clock generation and clock modes the high performance integrated clock generator meets the recommendations of itu-t g.735 and i.431 in case of input jitter tolerance, jitter transfer characteristic and output jitter. the following table shows the clock modes with the corresponding synchronization sources. the clock generator unit fulfills three main tasks. one is, to provide jitter free system clocks either derived from the line or from an external input. the other task is to produce a transmission clock for t1 applications (according to the recommendations). the third is to ensure output jitter characteristics in case jittered sclkx clock. the system clocks are provided by the dco1 (16 m, 8 m, 4/2 m, 8 k). the recovered route clock is first transformed to 2.048 mhz by a digital pll (in slave mode). the jitter transfer characteristic is given by a corner frequency of 6 hz and 20 db per decade fall off. the main task of dco2 is to generate the transmit clock. a 12.352 mhz crystal has to be connected to the dco2. the xslicer function is automatically enabled in the t1 mode. this results from the different frequencies of the line and system interface. the jitter transfer characteristics is given by a corner frequency of 6 hz and 20 db per decade fall off. mode internal los active sync input system clocks master no gnd free running (oscillator centered) master no 1.544 mhz synchronized on sync input (external 1.544 mhz) slave no gnd synchronized on line (rclk) slave no 1.544 mhz synchronized on line (rclk) slave yes gnd free running (oscillator centered) slave yes 1.544 mhz synchronized on sync input (external 1.544 mhz)
peb 2254 general functions and device architecture t1 semiconductor group 178 11.96 figure 45 transmit clock system framer/synchronizer the following functions are performed: ? synchronization on pulse frame ? synchronization on multiframe ? error indication when synchronization is lost. in this case, ais is automatically sent to the system side and remote alarm to the remote end if en/disabled. ? initiating and controlling of resynchronization after reaching the asynchronous state. this may be automatically done by the falc54 or user controlled via the microprocessor interface. ? detection of remote alarm (yellow alarm) indication from the incoming data stream. ? separation of service bits and data link bits. this information is stored in special status registers. ? detection of framed or unframed in band loop up/down code ? generation of various interrupt statuses of the receiver functions. these interrupts can be masked. ? generation of control signals to synchronize the crc checker, and the receive elastic store write control unit.
peb 2254 general functions and device architecture t1 semiconductor group 179 11.96 if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc multiframe according to the crc 6 procedure (refer to itu-t rec. g.704 ). these bits are compared with those check bits that are received during the next crc multiframe. if there is at least one mismatch, the crc error counter (16 bit) will be incremented. receive elastic store the received bit stream is stored in the receive elastic store. the memory is organized as a two-frame elastic buffer with a size of 48 8 bit. the functions are: ? clock adaption between system clock (sclkr) and internally generated route clock (rclk) ? compensation of input wander and jitter. maximum of wander amplitude (peak-to-peak): 142 ui in channel translation mode 0 78 ui in channel translation mode 1 (1 ui = 644 ns) ? frame alignment between system frame and receive route frame ? reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, channel-serial data which is circularly written to the elastic store using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock (sclkr) and the synchronous pulse ( sypr) in conjunction with the programmed offset values for the receive time-slot/clock-slot counters. after conversion into a serial data stream, the data is given out via port rdo. the 24 received channels are translated into the 32 system channels by a fixed organization. unequipped time-slots will be set to ff h . two bit rates (2048/4096 kbit/s) are selectable via the microprocessor interface. in 4096 kbit/s interface mode each channel will be sent out on two different channel- phases. each channel-phase which should be tri-stated is programmable. figure 46 gives an idea of operation of the receive elastic store: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the write pointer is within the slip limits (s +, s C). the values of s + and s C depend on the selected channel translation mode. if a slip condition is detected, a negative slip (the next received frame is skipped) or a positive slip (the previous received frame is read out twice) is performed at the system interface, depending on the difference between rclk and sclkr/4, i.e. on the position of pointer r and w within the memory.
peb 2254 general functions and device architecture t1 semiconductor group 180 11.96 figure 46 the receive elastic store as circularly organized memory receive signaling and maintenance controller the receive signaling controller can be programmed to operate in various signaling modes. the falc54 will perform the following signaling and data link methods: ? message oriented signaling also called common channel signaling ccs ? cas-bit robbing cas-br ? bit oriented messages in esf-dl ? 4 kbit/s data link access in f72 format the signaling information is carried in ts24 (ccs) or in one bit of every sixth frame for each channel which contains signaling information (bit robbing signaling). the signaling controller samples the bit stream which is output on pin rdo. in case of robbed bit signaling data is sampled on the receive line side clocked with the extracted receive route clock and stored in registers rs1-12. in case of common channel signaling the signaling procedure hdlc/sdlc will be supported. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending
peb 2254 general functions and device architecture t1 semiconductor group 181 11.96 on the selected address mode, the falc54 can perform a 1 or 2 byte address recognition. all frames with valid addresses are forwarded directly via the receive fifo (rfifo) to the system memory. the hdlc control-field, data in the i-field and an additional status byte are temporarily stored in the rfifo. in transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows the user specific protocol variations. the received data are stored in the rfifo. the falc54 offers the flexibility to extract data during certain time-slots which are defined via registers rtr1-4 and ttr1-4. any combination of time-slots can be programmed independent for the receive and transmit direction. if the falc54 is optioned for no signaling, the channels in the data stream from the system interface will pass the falc54 undisturbed. bit oriented messages the falc54 supports signaling and maintenance functions for t1 - primary rate interfaces using the extended super frame format. the device supports the dl-channel protocol for esf format according to t1.403 ansi specification or according to at&t tr54016. the hdlc- and bit oriented message (bom) -receiver can be switched on/off independently. to support the esf-dl protocol according at&t tr54016 or if the falc54 is used for hdlc formats only, the bom receiver has to be switched off (mode.brac=0). if hdlc- and bom-receiver has been switched on (mode:brac/hrac=1), an automatic switching between hdlc and bom mode is enabled. two different bom reception modes may be programmed (ccr1.brm). 4 kbit/s data link access in f72 format the falc54 supports the dl-channel protocol using the f72 (slc96) format in two ways. first: sampling of dl bits is done on a multiframe basis and stored in the registers rdl1-3. a receive multiframe begin interrupt is provided to read the received data dl bits. the contents of registers xdl1-3 is subsequently sent out on the transmit multiframe basis if it is enabled via fmr1.edl. a transmit multiframe begin interrupt requests for writing new information to the dl-bit registers. second: the dl bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller.the dl bits stored in the xfifo are inserted in the outgoing datastream, if it is enabled via ccr1.edlx. if ccr1.edlx is cleared a hdlc or no- hdlc frame could be sent or received via the rfifo / xfifo.
peb 2254 general functions and device architecture t1 semiconductor group 182 11.96 5.1.2 transmit path the inverse functions are performed for the transmit direction. the pcm data is received from the system internal highway at port xdi with 2048 kbit/s or 4096 kbit/s. the channel assignment is equivalent to the receive direction. all unequipped (idle) time-slots will be ignored. the contents of selectable channels (time-slots) can be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the three-byte registers icb1 icb3. internal multiplexing of (speech) data and signaling data can be disabled on a per channel basis (clear channel capability). this is also valid when using the internal signaling controller. latching of data is controlled by the system clock (sclkx) and the synchronous pulse (sypxq) in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters. transmit signaling controller similar to the receive signaling controller the same signaling methods and the same time-slot assignment are provided. the signaling information has to be written in the transmit fifo (xfifo). with a transmit frame command the signaling information will be sent in the corresponding signaling bit positions. the signaling will be internally multiplexed with the data at port xdi. if the transparent mode is selected, the falc54 supports the continuous transmission of the contents of the transmit fifo. the cyclic transmission continuous until the transmitter reset command (cmdr.sres) is issued or cmdr.xrep is reset. in case of ccs the signaling procedure hdlc/sdlc is supported with generation of preambles and flags, crc generation and bit-stuffing. for hdlc frames, the address and the control fields have to be entered in the xfifo as well. operating in hdlc or bom mode flags or idle may be transmitted as interframe timefill.
peb 2254 general functions and device architecture t1 semiconductor group 183 11.96 transmit elastic store the transmit elastic store with a size of 24 8 bit (one-frame) serves as a temporary store for the pcm data to adapt the system clock (sclkx) to the internally generated clock for the transmit data, and to re-translate channel structure used in the system to that of the line side. its optimal start position is initiated when programming the above offset values. a difference in the effective data rates of system side and transmit side may lead to an overflow/underflow of the transmit memory: thus, errors in data transmission to the remote end may occur. this error condition (transmit slip) is reported to the microprocessor via an interrupt status register. maximum wander amplitude (peak-to-peak): 58 ui in channel translation mode 0 46 ui in channel translation mode 1 (1 ui = 644 ns) because this is, under normal circumstances, a rare error condition no automatic action is taken by the transmit elastic store as opposed to the receive elastic store in the case of a positive or negative slip. in this case the falc54 requires a re-initialization of the transmit memory by re-programming the transmit time-slot counter. after that, this memory has its optimal start position. transmitter the serial bit stream is then processed by the transmitter which has the following functions: ? frame/multiframe synthesis of one of the four selectable framing formats ? insertion of service and data link information ? ais generation (blue alarm) ? remote alarm (yellow alarm) generation ? crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error or in case of activating per control bit ? generation of loop up/down code the multiframe boundries of the transmitter may be externally synchronized by using the xmfs pin. this feature is required if signaling-, service- and data link bits are routed through the switching network and are inserted in transmit direction via the system interface.
peb 2254 general functions and device architecture t1 semiconductor group 184 11.96 transmit line interface the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by pin xdi and the digital transmitter. similar to the receive line interface three different data types are supported: figure 47 transmitter configuration table 15 recommended transmitter configuration values ? ternary signal single rail data is converted into a ternary signal which is output on pins xl1 and xl2. selection between b8zs or simple ami coding with zero code suppression (b7 stuffing) is provided. b7 stuffing can be disabled on a per channel basis (clear channel capability). selected by fmr0.xc1/0 and lim1.drs = 0. ? dual rail data pcm(+), pcm(-) at multifunction ports xdop and xdon with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0.xc1=1 and lim1.drs = 1. unipolar data at port xoid will be transmitted in nrz (non return to zero) with 100 % duty cycle to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock xclk (1544 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. parameter characteristic impedance 100 w ds1 (6 db) t1 (18 db) r 1 ( 2.5 %) [ w ]55 t 2 : t 1 1 : ? 21 : ? 2
peb 2254 general functions and device architecture t1 semiconductor group 185 11.96 the falc54 includes a programmable pulse shaper to satisfy the requirements of the at&t technical advisory # 34 at the cross connect point for t1 applications. the amplitude of pulse shaper is individually programmable via the microprocessor interface to allow a maximum of different pulse templates. the line length is selected by programming the registers xpm2-0 as shown for typical values in table below. the values based on simulations with transformer ratio: 1:sqrt(2); cable: pulb 22awg (100 w ); serial resistors: 5 w . the xpm register values are in decimal. the transmitter requires an external step up transformer to drive the line. range in m xp04-xp00 xp14-xp10 xp24-xp20 xp34-xp30 0 - 35 29 27 10 3 25 - 65 29 28 10 3 55 - 95 31 28 10 2 85 - 125 31 27 13 2 115 - 155 31 26 13 2 145 - 185 31 26 13 3 175 - 210 31 25 14 3
peb 2254 general functions and device architecture t1 semiconductor group 186 11.96 transmit line monitor the transmit line monitor compares the transmit line pulses on xl1 and xl2 with the transmit input signals received on pins xl1m and xl2m. the monitor detects faults on the primary side of the transformer and protects the device from damage by setting the transmit line driver xl1/2 automatically in a high impedance state. faults on the secondary side may not be detected. to detect a short the configuration in figure 47 and the reset values of register xpm0-2 has to be fulfilled. otherwise the short detection could not be guaranteed. two conditions will be detected by the monitor: transmit line ones density (more than 31 consecutive zeros) and transmit line shorted. in both cases a transmit line monitor status change interrupt will be provided. figure 48 transmit line monitor configuration
peb 2254 general functions and device architecture t1 semiconductor group 187 11.96 5.1.3 additional functions clear channel capability for support of common t1 applications, clear channels can be specified via the 3-byte register bank ccb1 ccb3. in this mode the contents of selected channels will not be overwritten by bit robbing and zero code suppression (b7 stuffing) information. idle code insertion in transmit direction, the contents of selectable channels can be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the three-byte registers icb1 icb3. loop up/down code detection and generation the falc54 detects a framed or unframed loop up/actuate (00001)- and down/deactuate (001) pattern with bit error rates as high as 1/100. framing bits are excluded from loop code detection. status and interrupt-status bits will inform the user whether loop up - or loop down code was detected. in transmit direction replacing normal transmit data with loop up- or loop down code is done via control bits. however framing pattern will overwrite the loop code. transparent mode the described transparent modes are useful for loopbacks or for routing signaling information through the system interface. setting bit fmr4.tm switches the falc54 in transparent mode: in receive direction all bits in f-bit position of the incoming multiframe are forwarded to rdo and inserted in the fs/dl time-slot. in asynchronous state the received data can be transparently switched through if bit fmr2.dais is set. bit rdcf (bit 1 of fs/dl time-slot) indicates a dl bit. in transmit direction bit 8 of the fs/dl time-slot from the system internal highway (xdi) is inserted in the f-bit position of the outgoing frame. for complete transparency the internal signaling controller and line loop back has to be disabled and clear channels have to be defined via registers ccb1 ? 3. pulse density detection the falc54 examines the receive data stream on the pulse density requirement which is defined by ansi t1. 403. more than 15 consecutive zeros or less than n ones in each and every time window of 8(n+1) data bits where n=23 will be detected. violations of these rules are indicated by setting the status bit frs1.pden and the interrupt status bit
peb 2254 general functions and device architecture t1 semiconductor group 188 11.96 isr0.pden. generation of the interrupt status can be programmed either with the detection or with any change of state of the pulse density alarm (ipc.sci). system clocks and system pulses for transmitter and receiver the falc54 offers a flexible feature for system designers where different system clocks and system pulses are necessary. the interface to the receive system highway will be clocked via pin sclkr, while the interface to the transmit system highway is clocked via pin sclkx. the frequency on pin sclkr/x must fixed 8.192 mhz. the signals on pin sypr in conjunction with the assigned timeslot offset in register rc0 and rc1 will define the beginning of a frame on the receive system highway. the signal on pin sypx in conjunction with the assigned timeslot offset in register xc0 and xc1 will define the beginning of a frame on the transmit system highway. error performance monitoring the falc54 supports the error performance monitoring by detecting following alarms in the received data. ? framing errors ? crc errors ? code violations ? loss of frame alignment ? loss of signal ? alarm indication signal ? slip with a programmable interrupt mask (register imr4) all these error events could generate an errored second interrupt (es) if enabled. additionally a one second interrupt could be generated to indicate that the es interrupt has to be read. if the es interrupt is set the enabled alarm status bits or the error counters have to be examined. additionally an 16 bit wide errored block counter is realized. in esf format this counter will be incremented once per multiframe if a multiframe has been received with a crc error or an errored frame alignment has been detected. automatic remote alarm (yellow alarm) access if the receiver has lost its synchronization a remote alarm (yellow alarm) could be sent if enabled via bit fmr2.axra to the distant end. the remote alarm will be automatically generated in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be removed.
peb 2254 general functions and device architecture t1 semiconductor group 189 11.96 5.1.4 operating modes t1 general activated with bit fmr1.pmod = 1. pcm line bit rate : 1544 kbit/s single frame length : 193 bit, no. 1 193 framing frequency : 8 khz organization : 24 time-slots, no. 1 24 with 8 bits each, no. 1 8 and one preceding f bit selection of one of the four permissible framing formats is performed by bits fmr4.fm0 and fmr4.fm1. these formats are: f4 : 4-frame multiframe f12 : 12-frame multiframe (d4) esf : extended superframe f72 : 72-frame multiframe (slc96) the operating mode of the falc54 is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc54 implements all of the standard and/or common framing structures pcm 24 (t1, 1544 kbit/s) carriers. these are summarized in table 6, along with the signaling types applicable in each of the multiframe formats. general signaling refers to the support the falc54 provides for handling the data link or service bits, as the case may be, in the multiframe. table 16 summary of falc54 framing and supported signaling modes 4-frame multiframe 12-frame multiframe extended multiframe remote switch m. crc C C crc6 C signaling ccs cas-cc cas-br e.g. ch 24 e.g. ch 24 C e.g. ch 24 e.g. ch 24 e.g. ch 24 e.g. ch 24 e.g. ch 24 e.g. ch 24 general signaling fs bits C dl bits fs bits
peb 2254 general functions and device architecture t1 semiconductor group 190 11.96 ccs = common channel signaling cas-cc = channel associated signaling (common channel) cas-br = channel associated signaling (bit robbing) for ccs, cas-cc, and cas-br, different types of support are provided. note: the internal hdlc- or cas controller supports all signaling procedures like signaling frame synchronization / synthesis and signaling alarm detection. the next pages give a general description of the framing formats. after reset, the falc54 must be programmed with fmr1.pmod = 1. line interfacing ? ternary data with b8zs or ami (zcs) coding (selection via bit fmr0.xc1/0+ rc1/0). all code violations which do not correspond to zero code substitution rules are registrated by the code violation counter (cvc) with 16 bit length. if ami coding with zero code suppression (b7-stuffing) is selected, clear channels without b7-stuffing can be defined by programming registers ccb1 ccb3. ? single rail unipolar data with no zero suppression algorithm (fmr0.xc1or rc1 = 0). general aspects of synchronization synchronization status is reported via bit frs0.lfa (loss of frame alignment). framing errors (pulse frame and multiframe) are counted by the framing error counter fec. asynchronous state is reached if 2 out of 4 (bit fmr4.ssc1/0 = 00), or 2 out of 5 (bit fmr4.ssc1/0 = 01), or 2 out of 6 (bit fmr4.ssc1/0 = 10) framing bits (terminal framing or multiframing) are incorrect. if auto-mode is enabled, counting of framing errors is interrupted. the resynchronization procedure can be controlled by either one of the following procedure: ? automatically (fmr4.auto = 1). additionally, it may be triggered by the user by setting/resetting one of the bits fmr0.frs (force resynchronization) or fmr0.exls (external loss of frame). ? user controlled, exclusively, via above control bits in the non-auto-mode (fmr4.auto = 0).
peb 2254 general functions and device architecture t1 semiconductor group 191 11.96 addition for f12 and f72 format ft and fs bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately if programmed via bit fmr2.ssp. thus, a multiframe re-synchronization can be automatically initiated after detecting 2 errors out of 4/5/6 consecutive multiframing bits without influencing the state of the terminal framing. in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state is reached if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, the function of fmr0.exls is the same as above. setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. otherwise, a new frame search is started. this is useful in case the framing pattern that defines the pulseframe position is imitated periodically by a pattern in one of the speech/data channels.the f-bit error history (frs3.feh5 0) may be used in the decision whether to initiate resynchronization. the updating of these bits depends on the resynchronization mode: ? auto-mode: updating only during the synchronous state. ? non-auto mode: updating during the synchronous state and until one of the above control bits are set during the asynchronous state. the control bit fmr0.exls should be used first because it starts the synchronizer to search for a definite framing candidate. to observe actions of the synchronizer, the frame search restart flag frs0.fsrf is implemented. it toggles at the start of a new frame search if no candidate has been found at previous attempt. when resynchronization is initiated, the following values apply for the time required to achieve the synchronous state in case there is one definite framing candidate within the data stream: table 17 resynchronization timing frame mode avg. max. units f4 f12 esf f72 1.0 3.5 3.4 13.0 1.5 4.5 6.125 17.75 ms
peb 2254 general functions and device architecture t1 semiconductor group 192 11.96 figure 49 influences on synchronization status
peb 2254 general functions and device architecture t1 semiconductor group 193 11.96 figure 49 gives an overview of influences on synchronization status for the case of different external actions. activation of auto-mode and non-auto mode is performed via bit fmr4.auto. generally, for initiating resynchronization it is recommended to use bit: fmr0.exls first. in case where the synchronizer remains in the asynchronous state, bit fmr0.frs may be used to enforce it to lock onto the next framing candidate, although it might be a simulated one. general alarms ? ais (blue alarm): detection is flagged by bit frs0.ais. transmission is enabled via bit fmr1.xais. ? los (red alarm): detection is flagged at bit frs0.los. ? rai: remote alarm (yellow alarm) indication is flagged at bit frs0.rra. transmission is enabled via bit fmr4.xra. the type of remote alarm indication depends on the selected multiframe format. channel assignment there is one possibility provided for converting the 24 channels to the 32 time-slots on the system internal highway (refer to section interface to system internal highway). transparent mode setting bit fmr4.tm switches the falc54 in transparent mode: C in transmit direction bit 8 of the fs/dl time-slot from the system internal highway (xdi) is inserted C in the f-bit position of the outgoing frame. C in receive direction the framing bit is also forwarded to rdo and inserted in the fs/dl time-slot. bit rdcf (bit 1 of fs/dl time-slot) indicates a dl bit. general signaling a 4 khz dl clock which is output on port dlr and dlx marks the dl bit positions within the data stream at rdo and xdi.
peb 2254 general functions and device architecture t1 semiconductor group 194 11.96 signaling the selection of the signaling scheme is done via bit fmr1.sigm. ? ccs fmr1.sigm = 0 for common channel signaling, the use of time-slot 24 is recommended. the use of ccs is permitted for all multiframe formats. ? cas-cc fmr1.sigm = 0 instead of ccs the above channels may be used for carrying cas information. for positioning of the cas multiframe with respect to the selected multiframe structure, refer to dmi, part iii, 12.1. note: synchronization to and synthesis of the cas multiframe is not performed by the falc54. the use of cas-cc is permitted for all multiframe formats. ? cas-br fmr1.sigm = 1 the use of cas robbed bit signaling is applicable to f12, esf, and f72 multiframe format. especially when using the cas-br signaling schemes it could be necessary to define clear channels for data transmission. by programming registers ccb1 ccb3 they can be selected on a per channel basis. 5.1.4.1 4-frame multiframe the allocation of the ft bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in table 18 . the fs bit may be used for signaling. remote alarm (yellow alarm) is indicated by setting bit 2 to 0 in each channel. synchronization procedure for multiframe synchronization, the terminal framing bits (ft bits) are observed. the synchronous state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). table 18 4-frame multiframe structure frame number f t f s 1 2 3 4 1 C 0 C service bit service bit
peb 2254 general functions and device architecture t1 semiconductor group 195 11.96 5.1.4.2 12-frame multiframe normally, this kind of multiframe structure only makes sense when using the cas robbed bit signaling. in addition, ccs and cas-cc are also allowed. the multiframe alignment signal is located at the fs-bit position of every other frame (refer to table 19 ). there are two possibilities of remote alarm (yellow alarm) indication: ? bit 2 = 0 in each channel of a frame, selected with bit fmr0.sraf = 0 ? the last bit of the multiframe alignment signal (bit 1 of frame 12) changes from 0 to 1, selected with bit fmr0.sraf = 1. synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits) are observed, independently. further reaction on framing errors depends on the selected sync/resync procedure (via bit fmr2.ssp): ? fmr2.ssp = 0: terminal frame and multiframe synchronization are combined. two errors within 4/5/6 framing bits (via bits fmr4.ssc1/0) of one of the above will lead to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported via bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulseframing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. ? fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits will lead to the same reaction as described above for the combined mode. two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received.
peb 2254 general functions and device architecture t1 semiconductor group 196 11.96 table 19 12-frame multiframe structure frame number f t f s signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 1 C 0 C 1 C 0 C 1 C 0 C C 0 C 0 C 1 C 1 C 1 C 0 a b
peb 2254 general functions and device architecture t1 semiconductor group 197 11.96 5.1.4.3 extended superframe the use of the first bit of each frame for the multiframe alignment word, the data link bits, and the crc bits is shown in table 20 . additions crc6 inversion if enabled via bit rc0.crci, all crc bits of one outgoing extended multiframe are automatically inverted in case a crc error is flagged for the previous received multiframe. setting the bit rc0.xcrci will invert the crc bits before transmitted to the distant end. this function is logically ored with rc0.crci. table 20 extended superframe structure multiframe frame number f bits signaling channel designation multiframe bit number assignments fas dl crc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 2316 2509 2702 2895 3088 3231 3474 3667 3860 4053 4246 4439 C C C 0 C C C 0 C C C 1 C C C 0 C C C 1 C C C 1 m C m C m C m C m C m C m C m C m C m C m C m C C e 1 C C C e 2 C C C e 3 C C C e 4 C C C e 5 C C C e 6 C C a b c d
peb 2254 general functions and device architecture t1 semiconductor group 198 11.96 crc6 alarm interrupt as an extension of the crc6 checking algorithm the occurrence of a received crc6 error may set an interrupt status. the crc6 checking algorithm is enabled via bit fmr1.crc. if not enabled, all check bits in the transmit direction are set to 1. remote alarm (yellow alarm) is indicated by the periodical pattern 1111 1111 0000 0000 in the dl bits. all signaling schemes are applicable for this multiframing structure. for external access to the dl bits, refer to section general. synchronization procedure for multiframe synchronization the fas bits are observed. synchronous state is reached if at least one framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). in the synchronous state the framing bits (fas bits) are observed. two errors within 4/5/6 framing bits or two or more erroneous framing bits within one esf multiframe will lead to the asynchronous state. there are two multiframe synchronization modes selectable via fmr2.mcsp ? fmr2.mcsp = 0 : in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state will be reached again, if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. at the same time the internal framing pattern memory will be cleared and other possible framing candidates are lost. (identical to the synchronization procedure implemented in falc54 v1.1) ? fmr2.mcsp = 1 : this mode has been added in order to be able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs will lead to synchronization on the next candidate available. however, only the previously assumed candidate will discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). the synchronizer will be completely reset and initiates a new frame search, if there is no multiframing found. in this case bit fsr0.fsrf toggles.
peb 2254 general functions and device architecture t1 semiconductor group 199 11.96 ? 72-frame multiframe the 72-multiframe is an alternate use of the fs-bit pattern and is used for carrying data link information. this is done by stealing some of redundant multiframing bits after the transmission of the 12-bit framing header (refer to table 21 ). the position of a and b signaling channels (robbed bit signaling) is defined by zero-to-one and one-to-zero transitions of the fs bits and is continued when the fs bits are replaced by the data link bits. the use of this 24-bit data link channel, however, is not specified by the falc54. for access to these bits refer to section general. remote alarm (yellow alarm) is indicated by setting bit 2 to zero in each channel. an additional use of the d bits for alarm indication is user defined and must be done externally. in addition to cas-br, ccs and cas-cc are also applicable to this multiframe structure. synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits of the framing header) are observed independently. further reaction on framing errors depends on the selected sync/resync procedure (via bit fmr2.ssp): ? fmr2.ssp = 0: terminal frame and multiframe synchronization are combined two errors within 4/5/6 framing bits (via bits fmr4.ssc1/0) of one of the above will lead to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported via bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulseframing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. ? fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits will lead to the same reaction as described above for the combined mode. two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received.
peb 2254 general functions and device architecture t1 semiconductor group 200 11.96 table 21 72-frame multiframe structure frame number f t f fes signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 0 C 1 C 0 C 1 C 0 C 1 C C 0 C 0 C 0 C 1 C 1 C 1 b a 13 14 15 16 17 18 19 20 21 22 23 24 0 C 1 C 0 C 1 C 0 C 1 C C 0 C 0 C 0 C 1 C 1 C 1 b a 25 26 27 28 67 68 69 70 71 72 0 C 1 C 1 C 0 C 1 C C d C d C d C d C d b a
peb 2254 general functions and device architecture t1 semiconductor group 201 11.96 5.1.4.4 test functions there are two types of monitoring/testing functions: ? active tests which partly degrade the functionality (e.g. payload loop, remote loop, local loop, test loop for a single channel). ? diagnostics, during which the device is not operational (e.g. diagnostic loop of an entire trunk). payload loopback to perform an effective circuit test a line loop is implemented. when the payload loopback (fmr2.plb) is activated the received 192 bits of payload data will be looped back to the transmit direction. the framing bits, crc6 and dl bits are not looped. they are originated by the falc54 transmitter. when the plb is enabled the transmitter and the data on pins xl1/xdop and xl2/xdon are clocked with sclkr instead of sclkx. data on pin xdi are ignored. all the received data are processed normally. with bit fmr2.sais an ais could be sent to the system interface via pin rdo. figure 50 payload loop
peb 2254 general functions and device architecture t1 semiconductor group 202 11.96 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl+jatt. received data may be looped with or without the transmit jitter attenuator (fifo). figure 51 remote loop
peb 2254 general functions and device architecture t1 semiconductor group 203 11.96 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream will be undisturbed transmitted on the line. however an ais to the distant end could be enabled by setting fmr1.xais without influencing the data looped back to the system interface. note that enabling the local loop will usually invoke an out of frame error until the receiver can resync to the new framing. the serial code from the transmitter and receiver has to be programmed identically. figure 52 local loop
peb 2254 general functions and device architecture t1 semiconductor group 204 11.96 channel loop (loopback of time-slots) the channel loopback is selected via loop.ecbl= 1. each of the 24 channels may be selected for loopback from the system pcm input (xdi) to the system pcm output (rdo). this loopback is programmed for one channel at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route channel. for the channel test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested channel will disturb testing. these slips do not influence the other channels and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 53 channel loopback
peb 2254 general functions and device architecture t1 semiconductor group 205 11.96 alarm simulation alarm simulation does not affect the normal operation of the device, i.e. all channels remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: ? loss of signal (red alarm) ? alarm indication signal ais (blue alarm) ? loss of pulse frame ? remote alarm (yellow alarm) indication ? receive slip indication ? transmit slip indication ? framing error counter ? code violation counter (b8zs code) ? crc6 error counter some of the above indications are only simulated if the falc54 is configured in a mode where the alarm is applicable. the alarm simulation is controlled by the value of the alarm simulation counter: frs2.esc which is incremented by setting bit: fmr0.sim. clearing of alarm indications: C automatically for los, remote (yellow) alarm, ais, and loss of synchronization and C user controlled for slips by reading the corresponding interrupt status register isr3. C error counter have to be cleared by reading the corresponding counter registers. is only possible at defined counter steps of frs2.esc. for complete simulation (frs2.esc = 0), eight simulation steps are necessary.
peb 2254 general functions and device architecture t1 semiconductor group 206 11.96 5.2 signaling controller operating modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode register. 5.2.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the falc54 can perform a 1 or 2 byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the falc54 can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc. in case of a 1-byte address, ral1 and ral2 will be used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from a special register (rsis). as defined by the hdlc protocol, the falc54 perform the zero bit insertion/deletion (bit-stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least after 5 consecutive 1-s a 0 will appear. non-auto-mode (mode.mds2-1=01) characteristics: address recognition, flag - and crc generation/check, bit-stuffing all frames with valid addresses are forwarded directly via the rfifo to the system memory.
peb 2254 general functions and device architecture t1 semiconductor group 207 11.96 transparent mode 1 (mode.mds2-0=101) characteristics: address recognition, flag - and crc generation/check, bit-stuffing only the high byte of a 2-byte address field will be compared with registers rah1/2. the whole frame excluding the first address byte will be stored in rfifo. transparent mode 0 (mode.mds2-0=100) characteristics: flag - and crc generation/check, bit-stuffing no address recognition is performed and each frame will be stored in the rfifo. 5.2.2 extended transparent mode characteristics: fully transparent in no hdlc mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit-stuffing. this feature can be profitably used e.g for: ? specific protocol variations ? transmission of a bom frame ? test purposes data transmission is always performed out of the xfifo. in transparent mode, the receive data are shifted into the rfifo.
peb 2254 general functions and device architecture t1 semiconductor group 208 11.96 receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 54 receive data flow of falc
peb 2254 general functions and device architecture t1 semiconductor group 209 11.96 transmit data flow the frames can be transmitted as shown below. figure 55 transmit data flow of falc54 transmitting a hdlc frame via register cmdr.xtf, the address, the control fields and the data field have to be entered in the xfifo. if ccr3.xcrc is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will be closed automatically only with a (closing) flag. the falc54 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not.
peb 2254 general functions and device architecture t1 semiconductor group 210 11.96 5.2.3 special functions shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. preamble transmission if enabled via register ccr3, a programmable 8-bit pattern (register pre) is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent out. zero bit insertion is disabled during preamble transmission. to guarantee correct function the programmed preamble value should be different from receive address byte values. in bom-mode the msb of the preamble should be reset in order to achieve a quicker synchronization at the bom-receiver. after the preamble has been sent out the transmitter automatically inserts one synch-byte ff h before sending the contents of the transmit fifo. transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds2-0 = 111), the falc54 performs fully transparent data transmission and reception without hdlc framing, i.e. without ? flag insertion and deletion ? crc generation and checking ? bit-stuffing in order to enable fully transparent data transfer, bit mode.hrac has to be set and ff h has to be written to rah2. data transmission is always performed out of xfifo by directly shifting the contents of xfifo in the outgoing datastream. transmission is initiated by setting cmdr.xtf (04 h ). a synch-byte ff h is automatically sent before the first byte of the xfifo will be transmitted. received data is always shifted into rfifo.
peb 2254 general functions and device architecture t1 semiconductor group 211 11.96 cyclic transmission (fully transparent) if the extended transparent mode is selected, the falc54 supports the continuous transmission of the contents of the transmit fifo. after having written 1 to 32 bytes to xfifo, the command xrep.xtf via the cmdr register (bit 7 ? 0 = 00100100 = 24 h ) forces the falc54 to repeatedly transmit the data stored in xfifo to the remote end. note: the cyclic transmission continues until a reset command (cmdr: sres) is issued or with resetting cmdr.xrep, after which continuous 1-s are transmitted. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. crc on/off features as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3.xcrc. receive direction the received crc checksum is always assumed to be in the 2 (crc-itu) last bytes of a frame, immediately preceding a closing flag. if ccr3.rcrc is set, the received crc checksum will be written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if hdlc mode is selected, the limits for valid frame check are modified (refer to description of bit rsis.vfr). transmit direction if ccr3.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will only be closed automatically with a (closing) flag. the falc54 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. receive address pushed to rfifo the address field of received frames can be pushed to rfifo (first one/two bytes of the frame). this function is especially useful in conjunction with the extended address recognition. it is enabled by setting control bit ccr3.radd.
peb 2254 general functions and device architecture t1 semiconductor group 212 11.96 5.2.4 time-slot assigner the falc54 offers the flexibility to extract or insert data during certain time-slots which are defined via registers rtr1-4 and ttr1-4. any combination of time-slots can be programmed independent for the receive and transmit direction. table 22 time-slot assigner time-slots receive time-slot register transmit time-slot register rtr1.7 ttr1.7 0 rtr1.6 ttr1.6 1 rtr1.5 ttr1.5 2 rtr1.4 ttr1.4 3 rtr1.3 ttr1.3 4 rtr1.2 ttr1.2 5 rtr1.1 ttr1.1 6 rtr1.0 ttr1.0 7 rtr2.7 ttr2.7 8 rtr2.6 ttr2.6 9 rtr2.5 ttr2.5 10 rtr2.4 ttr2.4 11 rtr2.3 ttr2.3 12 rtr2.2 ttr2.2 13 rtr2.1 ttr2.1 14 rtr2.0 ttr2.0 15 rtr3.7 ttr3.7 16 rtr3.6 ttr3.6 17 rtr3.5 ttr3.5 18 rtr3.4 ttr3.4 19 rtr3.3 ttr3.3 20 rtr3.2 ttr3.2 21 rtr3.1 ttr3.1 22 rtr3.0 ttr3.0 23
peb 2254 general functions and device architecture t1 semiconductor group 213 11.96 5.2.5 bit oriented message mode the falc54 supports signaling and maintenance functions for t1 - primary rate interfaces using the extended super frame format. the device supports the dl-channel protocol for esf format according to t1.403-1989 ansi specification or according to at&t tr54016, 1989. the hdlc- and bit oriented message (bom) -receiver can be switched on/off independently. to support the esf-dl protocol according at&t tr54016 or if the falc54 is used for hdlc formats only, the bom receiver has to be switched off. if hdlc- and bom-receiver has been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. after reset or software-reset (cmdr.rres) the falc54 operates in hdlc mode. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the falc54 switches back to hdlc-mode. operating in bom-mode, the falc54 may receive an hdlc frame immediately, i.e. without any preceding flags. in bom-mode, the following byte format is assumed (the left most bit is received first). 111111110xxxxxx0 the falc54 uses the ff h byte for synchronization, the next byte is stored in rfifo (first bit received: lsb) if it starts and ends with a 0. bytes starting and ending with a 1 are not stored. if there are no 8 consecutive ones detected within 32 bits, an interrupt is generated. however, byte sampling is not stopped. rtr4.7 ttr4.7 24 rtr4.6 ttr4.6 25 rtr4.5 ttr4.5 26 rtr4.4 ttr4.4 27 rtr4.3 ttr4.3 28 rtr4.2 ttr4.2 29 rtr4.1 ttr4.1 30 rtr4.0 ttr4.0 31 table 22 time-slot assigner (contd) time-slots receive time-slot register transmit time-slot register
peb 2254 general functions and device architecture t1 semiconductor group 214 11.96 byte sampling in bom mode a) b) two different bom reception modes may be programmed (ccr1.brm). 10 byte packets: after storing 10 bytes in rfifo the receive status byte marking a bom frame (rsis.hfr) is added as the eleventh byte and an interrupt (isr0.rme) is generated. the sampling of data bytes continues and interrupts are generated every 10 bytes until an hdlc flag is detected. continuous reception: interrupts are generated every 32 (16, 4, 2) bytes. after detecting an hdlc flag, byte sampling is stopped, the receive status byte is stored in rfifo and an rme interrupt is generated. the user may switch between these modes at any time. byte sampling may be stopped by deactivating the bom receiver (mode.brac). in this case the receive status byte is added, an interrupt is generated and hdlc-mode is entered. whether the falc54 operates in hdlc or bom mode may be checked by reading the signaling status register (sis.bom). 1111 1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111 sync not stored new sync 1.byte stored 1.corrupted sync 2.byte stored 2.corrupted sync corrupted sync 1111 1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111 sync 1.byte stored 1.corrupted byte 2.byte stored 2.sync 3.byte stored 3.corrupted sync
peb 2254 general functions and device architecture t1 semiconductor group 215 11.96 5.2.6 4 kbit/s data link access in f72 format the falc54 supports the dl-channel protocol using the f72 (slc96) format in two ways. first: sampling of dl bits is done on a multiframe basis and stored in the registers rdl1-3. a receive multiframe begin interrupt is provided to read the received data dl bits. the contents of registers xdl1-3 is subsequently sent out on the transmit multiframe basis if it is enabled via fmr1.edl. a transmit multiframe begin interrupt requests for writing new information to the dl-bit registers. second: the dl bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller.the dl bits stored in the xfifo are inserted in the outgoing datastream, if it is enabled via ccr1.edlx. if ccr1.edlx is cleared a hdlc- or a transparent- frame could be sent or received via the rfifo / xfifo.
peb 2254 general functions and device architecture t1 semiconductor group 216 11.96 5.2.7 interface to system internal highway figure 56 data on rdo
peb 2254 general functions and device architecture t1 semiconductor group 217 11.96 figure 57 data on xdi
peb 2254 general functions and device architecture t1 semiconductor group 218 11.96 s: ccs/cas-cc signaling channel. the formats for fs/dl data transmission via the system interface are as follows: table 23 channel translation modes for pcm 24 speech channels time-slots c. translation mode 0 c. translation mode 1 fs/dl 1 2 3 C 4 5 6 C 7 8 9 C 10 11 12 C 13 14 15 C 16 17 18 C 19 20 21 C 22 23 s --- 24 fs/dl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 --- s C C C C C C C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
peb 2254 general functions and device architecture t1 semiconductor group 219 11.96 receive direction fs/dl bits on system internal receive highway (rdo), time-slot 0. figure 58 receive fs/dl bits on rdo each data bit is repeated for two frames. the reception of a new fs/dl bit is indicated by the r eceive d ata c hange f lag (normal operation: rdcf toggles; transparent mode enabled via bit fmr4.tm: rdcf is set, if the fs/dl bit-slot contains valid dl information). for further support in locating optionally defined subchannels the signals rmfb and xmfb may be used. in transparent mode fmr4.tm=1 every received fs/dl bit is transferred unchanged to the system interface. in order to get an undisturbed receiption even in the asynchronous state bit fmr2.dais has to be set. transmit direction fs/dl data on system internal transmit highway (xdi), time-slot 0. figure 59 transmit fs/dl bits on xdi
peb 2254 general functions and device architecture t1 semiconductor group 220 11.96 the fs/dl bit of every second frame is inserted into the transmit fs/dl-bit location of the assigned outgoing 193-bit frame. figure 60 supporting signals for ccs/cas-cc applications
peb 2254 general functions and device architecture t1 semiconductor group 221 11.96 figure 61 supporting signals for ccs/cas-cc applications
peb 2254 general functions and device architecture t1 semiconductor group 222 11.96 figure 62 supporting signals for cas-br applications
peb 2254 general functions and device architecture t1 semiconductor group 223 11.96 figure 63 signaling markers in 2/4-mbyte/s system interface mode an additional possibility exists for using the fs/dl bits for signaling, e.g. for ccs (see figure 63 ). for synchronizing this controller to the multiframe structure C the signals rmfb and xmfb, and C the signals dlr and dlx (4 khz dl clock) may be used. 4-mbyte system interface mode 2-mbyte/s interface mode
semiconductor group 224 11.96 peb 2254 operational description t1 6 operational description t1 reset the falc54 is forced to the reset state if a high signal is input at port res for a minimum period of 20 m s. during reset, all output stages except clk16m, clk12m, clk8m, clkx, fsc, xclk and rclk are tri-stated, all internal flip-flops are reset and most of the control registers are initialized with default values. after reset bit fmr1.pmod has to be set high and the device needs up to 20 m sec to settle up to the internal clocking. after fmr1.pmod has been set the configuration shown in table 24 is initialized. table 24 configuration if initialized after reset register initiated value meaning fmr0 00 h nrz coding, no alarm simulation. fmr1 fmr2 00 h 00 h pcm 24 mode, 4 mbit/s system interface mode, no ais transmission to remote end or system interface, payload loop off loop 00 h channel loop back are disabled. fmr4 fmr5 00 h 00 h remote alarm indication towards remote end disabled. lfa condition: 2 out of 4 framing bits, non-auto-synchronization mode, f12 multiframing, internal bit robbing access disabled xc0 xc1 00 h 00 h the transmit clock-slot offset is cleared. the transmit time-slot offset is cleared. rc0 rc1 00 h 00 h the receive clock slot offset is cleared. the receive time-slot offset is cleared. idle icb 1 ? 3 00 h 00 h idle channel code is cleared. normal operation (no idle channels selected). ccb 1 ? 300 h normal operation (no clear channel operation). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, frequency on pin clkx: 2.048 mhz, no los indication on pin rclk analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm2-0 9c h ,03 h ,00 h transmit pulse mask imr1-4 ff h all interrupts are disabled
semiconductor group 225 11.96 peb 2254 operational description t1 operational phase the falc54 is programmable via a microprocessor interface which enables access to 61 control and 35 status registers. after reset the falc54 has to be first initialized. general guidelines for initialization are described in section initialization. the status registers are read-only and are continuously updated. normally, the processor periodically reads the status registers to analyze the alarm status and signaling data. initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and dmi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 25 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, may be programmed simultaneously. the bit fmr1.pmod should always be kept high. rtr1-4 ttr1-4 00 h no time-slots selected mode 00 h signaling controller disabled pre rah1/2 ral1/2 00 h fd h ,ff h ff h ,ff h preamble cleared compare register for receive address cleared table 24 configuration if initialized after reset (contd) register initiated value meaning
semiconductor group 226 11.96 peb 2254 operational description t1 features like channel loop back, idle channel activation, clear channel activation, extensions for signaling support, alarm simulation, ? may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00hex. all control registers (except xfifo, xs1-12, cmdr, dec) are of type: read/write table 25 initialization parameters basic set up pcm 24 mode select specification of line interface and clock generation line interface coding loss of signal detection / recovery conditions system interface mode channel translation mode transmit offset counters receive offset counters ais to system interface fmr1.pmod = 1 lim0, lim1, xpm2-0 fmr0.xc1/0, fmr0.rc1/0 pcd, pcr,lim1 fmr1.imod fmr1.ctm xc0.xco, xc1.xto rc0.rco, rc1.rto fmr2.dais/sais operational set up pcm 24 select framing framing additions synchronization mode signaling mode fmr4.fm1/0 fmr1.crc, fmr0.sraf fmr4.auto, fmr4.ssc1/0, fmr2.mcsp,fmr2.ssp fmr1.sigm, fmr5.eibr, xc0.brm, mode, ccr1, ccr3, pre, rah1/2, ral1/2
semiconductor group 227 11.96 peb 2254 operational description t1 hdlc data transmission in transmit direction 2x32 byte fifo buffers are provided. after checking the xfifo status by polling the bit sis.xfw or after an interrupt isr1.xpr (transmit pool ready), up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can be started by issuing a xtf or xhf command via the command register. if enabled, a specified number of preambles (register pre) are optionally sent out before transmission of the current frame starts. if the transmit command does not include an end of message indication (cmdr.xme), the falc54 will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may be share a flag (enabled via ccr1.sflg), or may be transmitted as back-to-back frames, if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt isr1.xdu. the frame may be aborted per software cmdr.sres. the data transmission sequence, from the cpus point of view, is outlined in figure 64 .
semiconductor group 228 11.96 peb 2254 operational description t1 figure 64 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 65 . figure 65 interrupt driven transmission example
semiconductor group 229 11.96 peb 2254 operational description t1 data reception also 2 32 byte fifo buffers are provided in receive direction. there are different interrupt indications concerned with the reception of data: hdlc rpf (receive pool full) interrupt, indicating that a 32-byte-block of data can be read from rfifo and the received message is not yet complete. rme (receive message end) interrupt, indicating that the reception of one message is completed. the following figure 66 gives an example of a reception sequence, assuming that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 66 interrupt driven reception sequence example
semiconductor group 230 11.96 peb 2254 operational description t1 6.1 detailed register description t1 6.1.1 control register definition address register type comment 00 xfifo w transmit fifo 01 xfifo w transmit fifo 02 cmdr w command register 03 mode r/w mode register 04 rah1 r/w receive address high 1 05 rah2 r/w receive address high 2 06 ral1 r/w receive address low 1 07 ral2 r/w receive address low 2 08 ipc r/w interrupt port configuration 09 ccr1 r/w common configuration register 1 0a ccr3 r/w common configuration register 3 0b pre r/w preamble register 0c rtr1 r/w receive timeslot register 1 0d rtr2 r/w receive timeslot register 2 0e rtr3 r/w receive timeslot register 3 0f rtr4 r/w receive timeslot register 4 10 ttr1 r/w transmit timeslot register 1 11 ttr2 r/w transmit timeslot register 2 12 ttr3 r/w transmit timeslot register 3 13 ttr4 r/w transmit timeslot register 4 14 imr0 r/w interrupt mask register 0 15 imr1 r/w interrupt mask register 1 16 imr2 r/w interrupt mask register 2 17 imr3 r/w interrupt mask register 3 18 imr4 r/w interrupt mask register 4 19 1a fmr0 r/w framer mode register 0 1b fmr1 r/w framer mode register 1 1c fmr2 r/w framer mode register 2
semiconductor group 231 11.96 peb 2254 operational description t1 1d loop r/w channel loop back 1e fmr4 r/w framer mode register 4 1f fmr5 r/w framer mode register 5 20 xc0 r/w transmit control 0 21 xc1 r/w transmit control 1 22 rc0 r/w receive control 0 23 rc1 r/w receive control 1 24 xpm0 r/w transmit pulse mask 0 25 xpm1 r/w transmit pulse mask 1 26 xpm2 r/w transmit pulse mask 2 27 28 test w manufacturer test register 29 idle r/w idle channel code 2a xdl1 r/w transmit dl-bit register 1 2b xdl2 r/w transmit dl-bit register 2 2c xdl3 r/w transmit dl-bit register 3 2d ccb1 r/w clear channel register 1 2e ccb2 r/w clear channel register 2 2f ccb3 r/w clear channel register 3 30 icb1 r/w idle channel register 1 31 icb2 r/w idle channel register 2 32 icb3 r/w idle channel register 3 33 icb4 r/w idle channel register 4 34 lim0 r/w line interface mode 0 35 lim1 r/w line interface mode 1 36 pcd r/w pulse count detection 37 pcr r/w pulse count recovery 38 lim2 r/w line interface register 2 60 dec w disable error counter 62 test w manufacturer test register 6.1.1 control register definition (contd) address register type comment
semiconductor group 232 11.96 peb 2254 operational description t1 after reset all control registers except the xfifo and xs1-12 are initialized to defined values. transmit fifo (write) xfifo up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. writing data to xfifo can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr (or alls) interrupt. 70 xs1 w transmit signaling register 1 71 xs2 w transmit signaling register 2 72 xs3 w transmit signaling register 3 73 xs4 w transmit signaling register 4 74 xs5 w transmit signaling register 5 75 xs6 w transmit signaling register 6 76 xs7 w transmit signaling register 7 77 xs8 w transmit signaling register 8 78 xs9 w transmit signaling register 9 79 xs10 w transmit signaling register 10 7a xs11 w transmit signaling register 11 7b xs12 w transmit signaling register 12 70 xfifo xf7 xf0 (00/01) 6.1.1 control register definition (contd) address register type comment
semiconductor group 233 11.96 peb 2254 operational description t1 command register (read/write) value after reset: 00 h rmc receive message complete confirmation from cpu to falc54 that the current frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers will not be deleted. xrep transmission repeat if xrep is set to one together with xtf (write 24h to cmdr), the falc54 repeatedly transmits the contents of the xfifo (1 ? 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with an sres command or by resetting xrep. note: during cyclic transmission the xrep- bit has to be set with every write operation to cmdr. xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper will be reset. however the contents of the control registers will not be deleted. xhf transmit hdlc frame after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. 70 cmdr rmc rres xrep xres xhf xtf xme sres (02)
semiconductor group 234 11.96 peb 2254 operational description t1 xme transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the falc54 can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset the transmitter of the signaling controller will be reset. xfifo is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to xres an xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command depends on fmr1.imod. if fmr1.imod is set it takes 10 sclkx cycles and 5 sclkx cycles if fmr1.imod is cleared. therefore, if the cpu operates with a very high clock rate in comparison with the falc's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. mode register (read/write) value after reset: 00 h mds2-0 mode select the operating mode of the hdlc controller is selected. 000 ? reserved 001 ? reserved 010 ? 1 byte address comparison mode (ral1, 2) 011 ? 2 byte address comparison mode (rah1, 2 and ral1, 2) 100 ? no address comparison 101 ? 1 byte address comparison mode (rah1, 2) 110 ? reserved 111 ? no hdlc framing mode 1 70 mode mds2 mds1 mds0 brac hrac (03)
semiconductor group 235 11.96 peb 2254 operational description t1 brac bom receiver active switches the bom receiver to operational or inoperational state. 0 ? receiver inactive 1 ? receiver active hrac hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0 ? receiver inactive 1 ? receiver active receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 ? value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte 70 rah1 0 (04) 70 rah2 (05)
semiconductor group 236 11.96 peb 2254 operational description t1 receive address byte low register 1 (read/write) value after reset: ff h ral1 value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h unused bits have to be set to logical 0. vis masked interrupts visible 0 ? masked interrupt status bits are not visible. 1 ? masked interrupt status bits are visible. sci status change interrupt 0 interrupts will be generated either on coming or going of the internal interrupt source. 1 the following interrupts will be activated if enabled with detecting and recovering of the internal interrupt source: isr2.los isr2.ais isr0.pden 70 ral1 (06) 70 ral2 (07) 70 ipc vis sci ic1 ic0 (08)
semiconductor group 237 11.96 peb 2254 operational description t1 ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): common configuration register 1 (read/write) value after reset: 00 h sflg enable shared flags if this bit is set, the closing flag of a preceding frame simultaneously becomes the opening flag of the following frame. brm bom receive mode (significant in bom mode only) 0 ? 10 byte packets 1 ? continuous reception edlx enable dl bit access via the transmit fifo a one in this bit position enables the internal dl- bit access via the transmit fifo of the signaling controller. fmr1.edl has to be cleared to enable the sending of the contents of the xfifo on the ports xl1/2 or xdop/n. eits enable internal time-slot 0-31 signaling 0 internal signaling in time-slots 0-31 defined via registers rtr1-4 or ttr1-4 is disabled. 1 internal signaling in time-slots 0-31 defined via registers rtr1-4 or ttr1-4 is enabled. itf interframe time fill determines the idle (= no data to send) state of the transmit data coming from the signaling controller. 0 ? continuous logical 1 is output 1 ? continuous flag sequences are output (01111110 bit patterns) ioc1 ioc0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 ccr1 sflg brm edlx eits itf rft1 rft0 (09)
semiconductor group 238 11.96 peb 2254 operational description t1 rft1, rft0 rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft 1,0 can be changed dynamically C if reception is not running or C after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). see note . note: it is seen that changing the value of rft1,0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after an rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by an rmc command (see table below ): common configuration register 3 (read/write) value after reset: 00 h unused bits have to be set to logical 0. rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc4 . ? 0 rbc3 ? 0 rbc1,0 rbc0 70 ccr3 pre1 pre0 ept radd rcrc xcrc (0a)
semiconductor group 239 11.96 peb 2254 operational description t1 pre1, pre0 number of preamble repetition if preamble transmission is initiated, the preamble defined via register pre is transmitted 00 ? 1 times 01 ? 2 times 10 ? 4 times 11 ? 8 times. ept enable preamble transmission this bit enables transmission of a preamble. the preamble is started after interframe timefill transmission has been stopped and a new frame is to be transmitted. the preamble consists of an 8-bit pattern repeated a number of times. the pattern is defined via register pre, the number of repetitions is selected by bits pre0 and pre1. note: the shared flag feature is not influenced by preamble transmission. zero bit insertion is disabled during preamble transmission. radd receive address pushed to rfifo if this bit is set to 1, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode. rcrc receive crc on/off only applicable in non-auto mode. if this bit is set to 1, the received crc checksum will be written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for valid frame check are modified (refer to rsis.vfr ). xcrc transmit crc on/off if this bit is set to 1, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo). the transmitted frame will be closed automatically with a closing flag. note: the falc54 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not.
semiconductor group 240 11.96 peb 2254 operational description t1 preamble register (read/write) value after reset: 00 h pre0...pre7... preamble register this register defines the pattern which is sent out during preamble transmission (refer to register ccr3 ). lsb is sent first. it should be taken into consideration that zero bit insertion is disabled during preamble transmission. receive timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 timeslot register these bits define the received channels (time-slots) on the system highway to be extracted. additionally this registers will control the rsigm marker which can be forced high during the respective time-slots independent of bit ccr1.eits. a one in the rtr1-4 bits will sample the corresponding time-slot from the system highway if bit ccr1.eits is set. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? normal operation. 70 pre pre7 pre0 (0b) 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (0f)
semiconductor group 241 11.96 peb 2254 operational description t1 1 the contents of the selected time-slot will be stored in the rfifo. although the idle time-slots can be selected. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on pin rsigm. transmit timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 transmit timeslot register these bits define the transmit channels (time-slots) on the system highway to be inserted. additionally this registers will control the xsigm marker which can be forced high during the respective time-slots independent of bit ccr1.eits. a one in the ttr1-4 bits will insert the corresponding time-slot on the system highway if bit ccr1.eits is set. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? normal operation. 1 the contents of the selected time-slot will be inserted in the outgoing data stream. although the idle time-slots can be selected. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (13)
semiconductor group 242 11.96 peb 2254 operational description t1 interrupt mask register 04 value after reset: ff h , ff h , ff h , ff h ,ff h imr0...imr4... interrupt mask register each interrupt source can generate an interrupt signal at port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr04 sets the mask active for the interrupt status in isr03. masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. after reset, all interrupts are dis abled. framer mode register 0 (read/write) value after reset: 00 h xc1xc0 transmit code serial code transmitter is different programmable from the receiver. 00 nrz (optical interface) 01 not assigned 10 ami coding with zero code suppression (zcs, b7 - stuffing). disabling of the zcs is done by activating the clear channel mode via register ccb1-3. (ternary or digital interface) 11 b8zs code (ternary or digital dual rail interface) 70 imr0 rme rfs isf rmb rsc crc6 pden rpf (14) imr1 case rdo alls xdu xmb xlsc xpr (15) imr2 far lfa mfar lmfa ais los rar ra (16) imr3 es sec xslp llbsc sln slp (17) imr4 lfa fer cer ais los cve slip (18) 70 fmr0 xc1 xc0 rc1 rc0 frs sraf exls sim (1a)
semiconductor group 243 11.96 peb 2254 operational description t1 rc1rc0 receive code serial code receiver is different programmable from the transmitter. 00 nrz (optical interface) 01 not assigned 10 ami coding with zero code suppression (zcs, b7 - stuffing), (ternary or digital dual rail interface) 11 b8zs code (ternary or digital dual rail interface) frs force resynchronization a transition from low to high will force the frame aligner to execute a resynchronization of the pulse frame. in the asynchronous state, a new frame position is assumed at the next candidate if there is one. otherwise, a new frame search with the meaning of a general reset is started. in the synchronous state this bit will have the same meaning as bit fmr0.exls except if fmr2.mcsp=1. sraf select remote (yellow) alarm format for f12 and esf format 0 f12: bit2 = 0 in every channel. esf: pattern 1111 1111 0000 0000 in data link channel. 1 f12: fs bit of frame 12. esf: bit2 = 0 in every channel exls external loss of frame with a low to high transition a new frame search will be started. this has the meaning of a general reset of the internal frame alignment unit. synchronous state is reached only if there is one definite framing candidate. in the case of multiple candidates, the setting of the bit fmr0.frs forces the receiver to lock onto the next available framing position. sim alarm simulation setting/resetting this bit initiates internal error simulation of: ais (blue alarm), loss of signal (red alarm), loss of frame alignment, slip, framing errors, crc errors, code violations. the error counters fec, cvc, cec, ebc will be incremented. the selection of simulated alarms is done via the error simulation counter: frs2.esc2-0 which will be incremented with each setting of bit fmr0.sim. for complete checking of the alarm indications eight simulation steps are necessary (frs2.esc2-0 = 0 after a complete simulation).
semiconductor group 244 11.96 peb 2254 operational description t1 framer mode register 1 (read/write) value after reset: 00 h ctm channel translation mode 0 channel translation mode 0 1 channel translation mode 1 sigm select signaling mode 0 ccs/cas-cc mode 1 cas-br mode for selection of clear channels refer clear channel register ccb1ccb3. edl enable dl-bit access via register xdl1-3 only applicable in f4, f24 or f72 frame format. 0 normal operation. the dl-bits will be taken from system highway or if enabled via ccr1.edlx from the xfifo of the signaling controller. 1 dl-bit register access. the dl-bit information will be taken from the registers xdl1-3 and will overwrite the dl-bits received at the system highway (pin xdi) or the internal xfifo of the signaling controller. however, transmitting contents of registers xdl1-3 will be disabled if transparent mode is enabled (fmr4.tm). pmod pcm mode for t1 application this bit must be set high. switching into t1 mode the device needs up to 20 m sec to settle up to the internal clocking. 1 pcm 24 mode. crc enable crc6 this bit is only significant when using the esf format. 0 ? crc6 check/generation disabled. for transmit direction, all crc bit positions are set to 1. 1 ? crc6 check/generation enabled. 70 fmr1 ctm sigm edl pmod crc ecm imod xais (1b)
semiconductor group 245 11.96 peb 2254 operational description t1 ecm error counter mode the function of the error counters (fec,cec,cvc,ebc) will be determined by this bit. 0 ? before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters will be reset with the rising edge of the corresponding bits in the dec register. 1 every second the error counter will be latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided. imod system interface mode 0 4 mbit/s mode 1 2 mbit/s mode xais transmit ais towards remote end sends ais (blue alarm) via ports: xl1, xl2 towards the remote end. if local loop mode is enabled the transmitted data are looped back to the system internal highway without any changes. framer mode register 2 (read/write) value after reset: 00 h mcsp... multiple candidates synchronization procedure only valid if f24 format is selected: 0... normal operation (identical to the synchronization procedure implemented in falc54 v1.1). 1... a one will enable a synchronization mode which is able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs will lead to synchronization on the next candidate available. however, only the previously assumed 70 fmr2 mcsp ssp dais sais plb axra exze (1c)
semiconductor group 246 11.96 peb 2254 operational description t1 candidate will discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). ssp select sync/resync procedure only valid if f12 or f72 format is selected: 0 specified number of errors in both ft framing and fs framing lead to loss of sync (frs0.lfa is set). in the case of fs bit framing errors, bit frs0.lmfa is set additionally. a complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. 1 specified number of errors in ft framing has the same effect as above. specified number of errors in fs framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (frs0.lmfa is set). dais disable ais to system interface 0 ais is automatically inserted into the data stream to rdo if falc54 is in asynchronous state. 1 automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais send ais towards system interface sends ais (blue alarm) via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loop back 0 ? normal operation 1 the payload loopback will loop the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received at port xdi, sypxq and xmfs will be ignored. with fmr4.tm=1 all 193 bits per frame will be looped back. if fmr4.tm=0 the dl- or fs- or crc- bits will be generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. during payload loop is active the receive time-slot offset (registers rc1/0) should not be changed.
semiconductor group 247 11.96 peb 2254 operational description t1 axra automatic transmit remote alarm 0 ? normal operation 1 the remote alarm (yellow alarm) bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be reset. exze excessive zeros detection enable selects error detection mode in the bipolar receive bit stream. 0 only bipolar violations are detected. 1 bipolar violations and zero strings of 8 or more contiguous zeros in b8zs code or more than 15 contiguous zeros in ami code are detected additionally and counted in the code violation counter cvc. loop (read/write) value after reset: 00 h rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the disable ais to system interface feature (fmr2.dais) to realize undisturbed transparent reception. eclb enable channel loop back 0 disables the channel loop back. 1 enables the channel loop back selected by this register. cla4cla0 channel address for loop back cla = 124 selects the channel. during loop back, the contents of the associated outgoing channel at ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed in register idle. 70 loop rtm eclb cla4 cla0 (1d)
semiconductor group 248 11.96 peb 2254 operational description t1 framer mode register 4 (read/write) value after reset: 00 h ais3 select ais condition 0 ais (blue alarm) is indicated (frs0.ais) when two or less zeros in the received bit stream are detected in a time interval of 12 frames (f4, f12, f72) or 24 frames (esf). 1 ais (blue alarm) detection is only enabled when falc54 is in asynchronous state. the alarm is indicated (frs0.ais) when C three or less zeros within a time interval of 12 frames (f4, f12, f72), or C five or less zeros within a time interval of 24 frames (esf) are detected in the received bit stream. tm transparent mode setting this bit enables the transparent mode: C in transmit direction bit 8 of every fs/dl time-slot from the system internal highway (xdi) is inserted in the f-bit position of the outgoing frame. internal framing generation, insertion of crc and dl data is disabled. C in receive direction the framing bit is also forwarded to rdo and inserted in the fs/dl timeslot. bit rdcf (bit 1 of fs/dl time-slot) indicates a dl bit. xra transmit remote alarm (yellow alarm) if high, remote alarm is sent via pcm route. clearing the bit will remove the remote alarm pattern. remote alarm indication depends on the multiframe structure as follows: f4: bit2 = 0 in every speech channel f12: C fmr0.sraf = 0: bit2 = 0 in every speech channel C fmr0.sraf = 1: fs-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111 1111 0000 0000 in data link channel C fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel 70 fmr4 ais3 tm xra ssc1 ssc0 auto fm1 fm0 (1e)
semiconductor group 249 11.96 peb 2254 operational description t1 ssc1/0 select sync conditions loss of frame alignment (frs0.lfa or opt. frs0.lmfa) is declared if 00 = 2 out of 4 framing bits 01 = 2 out of 5 framing bits 10 = 2 out of 6 framing bits in f4/12/72 format 10 = 2 out of 6 framing bits per multiframe period in esf format 11 = reserved are incorrect. it depends on the selected multiframe format and optionally on bit fmr2.ssp which framing bits are observed: f4: ft bits ? frs0.lfa f12, f72: ssp = 0: ft bits ? frs0.lfa: fs bits ? frs0.lfa and frs0.lmfa ssp = 1:ft ? frs0.lfa fs ? frs0.lmfa esf: esf framing bits ? frs0.lfa auto enable auto resynchronization 0 the receiver will not resynchronize automatically. starting a new synchronization procedure is possible via the bits: fmr0.exls or fmr0.frs. 1 auto-resynchronization is enabled. fm1fm0 select frame mode fm = 0: 12-frame multiframe format (f12, d3/4) fm = 1: 4-frame multiframe format (f4) fm = 2: 24-frame multiframe format (esf) fm = 3: 72-frame multiframe format (f72, remote switch mode) framer mode register 5 (read/write) value after reset: 00 h eibr enable internal bit robbing access 0 normal operation. 1 a one in this bit position will cause the transmitter to send the bit robbing signaling information stored in the xs1-12 (esf) resp. xs1-6 (f12/72) registers in the corresponding time slots. 70 fmr5 eibr xld xlu (1f)
semiconductor group 250 11.96 peb 2254 operational description t1 xld transmit loop down code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the loop down code: 001 continuously until this bit is reset. the loop down code will be overwritten by the framing/dl/crc bits. xlu transmit loop up code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the loop up code 00001 continuously until this bit is reset. the loop up code will be overwritten by the framing/dl/crc bits. transmit control 0 (read/write) value after reset: 00 h brm enable bit robbing marker a one in this bit will mark the robbed bit positions on the system highway. rsigm marks the receive and xsigm marks the transmit robbed bits. only valid if robbed bit signaling is enabled (fmr1.sigm=1). mfbs enable pure multiframe begin signals only valid if esf or f72 format is selected. if set, signals rmfb and xmfb indicate only the multiframe begin. additional pulses (every 12 frames) are disabled. sfrz select freeze output 0 ? signal rfsp is output on port rfsp/freeze. 1 ? freeze status signal will be output on port rfsp/freeze. xco2xco0 transmit clock-slot offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse at port sypxq is active (see figure 57 ). 70 xc0 brm mfbs sfrz xco2 xco0 (20)
semiconductor group 251 11.96 peb 2254 operational description t1 transmit control 1 (read/write) value after reset: 00 h xcos transmit clock offset shift 0 the delay t between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is an even number in the range from 0 to 1022 sclkx cycles. 1 the delay t is an odd number in the range from 1 to 1023 sclkx cycles. xto5xto0 transmit time-slot offset initial value loaded into the transmit time-slot counter at the trigger edge of sclkx when the synchronous pulse at port sypxq is active (see figure 57 ). a write access to this address resets the transmit speech memory to its basic starting position. therefore, updating the value should only be done when the falc54 is initialized or when a transmit slip indicates a defective clock system. receive control 0 (read/write) value after reset: 00 h rcos receive clock offset shift 0 the delay t between the beginning of time-slot 0 and the initial edge of sclkr (after sypr goes active) is an even number in the range from 0 to 1022 sclkr cycles. 1 the delay t is an odd number in the range from 1 to 1023 sclkr cycles. 70 xc1 xcos xto5 xto0 (21) 70 rco rcos sics crci xcrci rdis rco2 rco1 rco0 (22)
semiconductor group 252 11.96 peb 2254 operational description t1 sics system interface channel select only applicable if bit fmr1.imod (4 mhz system interface) is set. 0 ? received data is output on port rdo in the first channel phase. data in the second channel phase is tri-stated. data on pin xdi is sampled only in the first channel phase. data in the second channel phase is ignored. 1 ? data on port rdo is output in the second channel phase. the first channel phase is tri-stated. sampling of data from the system highway is done in the second channel phase. crci automatic crc6 bit inversion if set, all crc bits of one outgoing extended multiframe are inverted in case a crc error is flagged for the previous received multiframe. this function is logically ored with rc0.xcrci. xcrci transmit crc6 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense 0 ? inputs: rdip, rdin active low, input roid is active high 1 ? inputs: rdip, rdin active high, input roid is active low rco2rco0 receive clock-slot offset initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 56 ). receive control 1 (read/write) value after reset: 00 h rram receive remote alarm mode the conditions for remote (yellow) alarm (frs0.rra) detection can be selected via this bit to allow detection even in the presence of ber 10**-3: rram = 0 detection 70 rc1 rram rto5 rto0 (23)
semiconductor group 253 11.96 peb 2254 operational description t1 f4: bit2 = 0 in every speech channel per frame. f12: C fmr0.sraf = 0: bit2 = 0 in every speech channel per frame. C fmr0.sraf = 1: s-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111 1111 0000 0000 in data link channel C fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel per frame. release the alarm will be reset when above conditions are no longer detected. rram = 1 detection f4: bit2 = 0 in 255 consecutive speech channels. f12: C fmr0.sraf = 0: bit 2 = 0 in 255 consecutive speech channels. C fmr0.sraf = 1: s-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111 1111 0000 0000 in data link channel C fmr0.sraf = 1: bit 2 = 0 in 255 consecutive speech channels f72: bit 2 = 0 in 255 consecutive speech channels. release depending on the selected multiframe format the alarm will be reset when falc54 does not detect C the bit 2 = 0 condition for three consecutive pulseframes (all formats if selected), C the fs bit condition for three consecutive multiframes (f12), C the dl pattern for three times in a row (esf). rto5rto0receive time-slot offset initial value loaded into the receive time-slot counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 56 ). transmit pulse-mask 20 (read/write) value after reset: 9c h , 03 h , 00 h 70 xpm0 xp12 xp11 xp10 xp04 xp03 xp02 xp01 xp00 (24)
semiconductor group 254 11.96 peb 2254 operational description t1 the transmit pulse shape which is defined in itu-t g.703 will be output on pins xl1 and xl2. the level of the pulse shape can be programmed via registers xpm2-0 to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape will be internally devided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value will define the level of the analog voltage on pins xl1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape.the four 5 bit values will be sent in the following sequence: xp04-00: first pulse shape level xp14-10: second pulse shape level xp24-20: third pulse shape level xp34-30: fourth pulse shape level changing the lsb of each subpulse in registers xpm2-0 will change the amplitude of the differential voltage on xl1/2 by approximately 110 mv. the xpm- values are valid for the following external circuitry: transformer ratio: 1:sqrt(2); cable: pulb 22awg (100 w ); serial resistors: 5 w . ds1: the xpmxx register values shown in the table below are in decimal format. t1- 18 db: the xpmxx register values shown in the table below are in decimal format. xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (25) xpm2 xlhp xlt daxlt xp34 xp33 xp32 xp31 (26) range in m xp04-xp00 xp14-xp10 xp24-xp20 xp34-xp30 0 - 35 29 27 10 3 25 - 65 29 28 10 3 55 - 95 31 28 10 2 85 - 125 31 27 13 2 115 - 155 31 26 13 2 145 - 185 31 26 13 3 175 - 210 31 25 14 3 xp04-xp00 xp14-xp10 xp24-xp20 xp34-xp30 24 22 7 3
semiconductor group 255 11.96 peb 2254 operational description t1 xlhp transmit line high power 0 ... normal operation. 1 ... with this bit the output current capability of the transmit line xl1 and xl2 can be influenced. connecting low impedances to the outputs xl1/xl2 this bit should be set to one to avoid instable pulse shapes. setting this bit has no influence on the voltage levels of the pulse shape. xlt transmit line tri-state 0 ? normal operation 1 ? transmit line xl1/xl2 or xdop/xdon are switched into high impedance state. if this bit is set the transmit line monitor status information will be frozen. daxlt... disable automatic tristating of xl1/2 0... normal operation. if a short is detected on pins xl1/2 the transmit line monitor will set the xl1/2 outputs into a high impedance state. 1... if a short is detected on pins xl1/2 an automatic setting these pins into a high impedance state (by the xl-monitor) will be disabled. idle channel code register (read/write) value after reset: 00 h idl7idl0 idle channel code if channel loop back is enabled by programming the register loop.eclb = 1, the contents of the assigned outgoing channel at ports xl1/xl2 resp. xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels of the outgoing pcm frame selected via the idle channel registers icb1icb3. idl7 will be transmitted first. 70 idle idl7 idl0 (29)
semiconductor group 256 11.96 peb 2254 operational description t1 transmit dl-bit register 1-3 (read/write) value after reset: 00 h , 00 h , 00 h xdl1xdl3 transmit fs/dl-bit data the dl-bit register access is enabled by setting bits fmr1.edl = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xdl1-3 will be copied into a shadow register. the contents will subsequently sent out in the data stream of the next outgoing multiframe if no transparent mode is enabled. xdl10 will be sent out first. in f4 frame format only xdl10+xdl11 will be transmitted. in f24 frame format xdl10-xdl23 will be shifted out. in f72 frame format xdl10-xdl37 will be transmitted. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information will be ignored, current contents will be repeated. clear channel register (read/write) value after reset: 00 h , 00 h , 00 h ch1ch24 channel selection bits 0 normal operation. bit robbing information and zero code suppression (zcs, b7 stuffing) may change contents of the selected speech/data channel if assigned modes are enabled via bits fmr1.sigm and fmr0.xc1/0. 1 clear channel mode. contents of selected speech/data channel will not be overwritten by bit robbing and zcs information. transmission of channel assigned signaling and control of pulse density is applied by the user. 70 xdl1 xdl17 xdl16 xdl15 xdl14 xdl13 xdl12 xdl11 xdl10 (2a) xdl2 xdl27 xdl26 xdl25 xdl24 xdl23 xdl22 xdl21 xdl20 (2b) xdl3 xdl37 xdl36 xdl35 xdl34 xdl33 xdl32 xdl31 xdl30 (2c) 70 ccb1 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 (2d) ccb2 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 (2e) ccb3 ch17 ch18 ch19 ch20 ch21 ch22 ch23 ch24 (2f)
semiconductor group 257 11.96 peb 2254 operational description t1 idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic1ic24 idle channel selection bits these bits define the channels (time-slots) of the outgoing pcm frame to be altered. 0 normal operation. 1 idle channel mode. the contents of the selected channel is overwritten by the idle channel code defined via register idle. line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode 0 ? output signals xdop/xdon are half bauded (normal operation). 1 ? output signals xdop/xdon are full bauded. xdos transmit data output sense 0 ? output signals xdop/xdon are active low (normal operation). 1 ? output signals xdop/xdon are active high. scl1scl0 select clock output 00 ? output frequency at pin clkx : 2048 khz active high 01 ? output frequency at pin clkx : 2048 khz active low 10 ? output frequency at pin clkx : 4096 khz active high 11 ? output frequency at pin clkx : 4096 khz active low 70 icb1 ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 (30) icb2 ic9 ic10 ic11 ic12 ic13 ic14 ic15 ic16 (31) icb3 ic17 ic18 ic19 ic20 ic21 ic22 ic23 ic24 (32) icb4 reserved (33) 70 lim0 xfb xdos scl1 scl0 eqon elos ll mas (34)
semiconductor group 258 11.96 peb 2254 operational description t1 eqon receive equalizer on 0 ? 6 db receiver 1 ? 18 db equalizer on elos enable loss of signal 0... normal operation. the extracted receive clock is output via pin rclk. 1... in case of loss of signal (frs0.los=1) the rclk is set high. if frs0.los=0 the received clock is output via rclk. ll local loop 0 ? normal operation 1 ? local loop active. the local loopback mode disconnects the receive lines rl1/rl2 resp. rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream will be undisturbed transmitted on the line. receiver and transmitter coding must be identical. mas master mode 0 ? slave mode 1 ? master mode on. if this bit is set and the sync pin is connected to v ss the falc54 works as a master for the system. the internal dcos of the jitter attenuator are centered and the system clocks which are output via clk8m/clkx are stable (divided from the dco frequencies). if a clock (1.544 mhz or 2.048 mhz) is detected at the sync pin the falc54 synchronizes automatically to this clock. the production tolerance is approximately 30 ppm of the crystal frequency if c load = 15 pf. line interface mode 1 (read/write) value after reset: 00 h efsc enable frame synchronization pulse 0 = the transmit clock is output via pin xclk. 70 lim1 efsc ril2 ril1 ril0 dcoc jatt rl drs (35)
semiconductor group 259 11.96 peb 2254 operational description t1 1 = pin xclk provides a 8 khz frame synchronization pulse which is active high for one 2 mhz cycle (pulse width = 488 ns). ril2ril0 receive input threshold only valid if analog line interface is selected (lim1.drs=0). no signal will be declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2-0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal will be declared is programmable via the ril2-0 bits. 000 = 1.36 v 001 = 1.04 v 010 = 0.84 v 011 = 0.62 v 100 = 0.43 v 101 = 0.32 v 110 = 0.22 v 111 = not assigned dcoc ? dco1 control a one in this bit position will enable to synchronize the internal generated systems clocks from dco1 to an external 2 mhz clock provided on pin sync. jattrl... transmit jitter attenuator / remote loop 00 = normal operation. the transmit jitter attenuator is disabled. transmit data will bypass the buffer. 01 = remote loop active without transmit jitter attenuator enabled. transmit data will bypass the buffer. 10 = not assigned 11 = remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid will be sent jitter free on ports xl1/2 or xdop/n or xoid. drs dual rail select 0 = the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 = the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon.
semiconductor group 260 11.96 peb 2254 operational description t1 pulse count detection register (read/write) value after reset: 00 h pcd7pcd0 pulse count detection a los alarm (red alarm) will be detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and can be calculated as follows: t= 16(n+1) ; with 0 =< n =< 255. the maximum time is: 256 16 648 ns = 2.65 ms. every detected pulse will reset the internal pulse counter. the counter will be clocked with the receive clock rclk. pulse count recovery (read/write) value after reset: 00 h pcr7pcr0 pulse count recovery a los alarm (red alarm) will be cleared if a pulse density is detected in the received bit stream.the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n+1 ; with 0 =< n =< 255. the time interval starts with the first detected pulse transition. with every received pulse a counter will be incremented and the actual counter is compared with the contents of pcr register. if the pulse number >= the pcr value the los alarm will be reset otherwise the alarm will still be active. in this case the next detected pulse transition will start a new time interval. additional loss of signal recovery conditions may be selected by register lim2.los2/1. 70 pcd pcd7 pcd0 (36) 70 pcr pcr7 pcr0 (37)
semiconductor group 261 11.96 peb 2254 operational description t1 line interface mode 2 (read/write) value after reset: 00 h los2/1 loss of signal recovery condition 00 the los alarm will be cleared if the predefined pulse density (register pcr) is detected during the time interval which is defined by register pcd. 01 additionally to the recovery condition described above a los alarm will only be cleared if the pulse density is fulfilled and no more than 15 contigious zeros are detected during the recovery interval. (according to tr-nwt 499). 10 clearing a los alarm will be done if the pulse density is fulfilled and no more than 99 contigious zeros are detected during the recovery interval. (according to tr-nwt 820). 11 not assigned disable error counter (write) value after reset: 00 h dcec disable crc error counter only valid if fmr1.ecm is reset. this bit has to be set before reading the crc error counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the crc error counter is latched and then cleared. debc disable errored block counter only valid if fmr1.ecm is reset. this bit has to be set before reading the errored block counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the errored block counter is latched and then cleared. 70 lim2 los2 los1 (38) 70 dec dcec debc dcvc dfec (60)
semiconductor group 262 11.96 peb 2254 operational description t1 dcvc disable code violation counter only valid if fmr1.ecm is reset. this bit has to be set before reading the code violation counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the code violation counter is latched and then cleared. dfec disable framing error counter only valid if fmr1.ecm is reset. this bit has to be set before reading the framing error counter. it will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of this bit the framing error counter is latched and then cleared.
semiconductor group 263 11.96 peb 2254 operational description t1 transmit signaling register (write) value after reset: not defined transmit signaling register 1-12 the transmit signaling register access is enabled by setting bit fmr5.eibr = 1. each register contains the bit robbing information for 8 ds0 channels. with the transmit cas empty interrupt isr1.case the contents of these registers will be copied into a shadow register. the contents will subsequently sent out in the corresponding bit positions of the next outgoing multiframe. xs1.0 will be sent out first in channel 1 frame 1 and xs12.7 will be sent out last. in the esf format the transmit cas empty interrupt isr1.case requests that these registers should be serviced within the next 3 ms. in f12/f72 format only signaling channel stored in xs1-6 registers will be sent out, registers xs6-12 are ignored. in this framing modes the interrupt isr1.case will be active every 1.5 ms. if requests for new information are ignored, current contents will be repeated. 70 xs1 a8 a7 a6 a5 a4 a3 a2 a1 (70) xs2 a16 a15 a14 a13 a12 a11 a10 a9 (71) xs3 a24 a23 a22 a21 a20 a19 a18 a17 (72) xs4 b8 b7 b6 b5 b4 b3 b2 b1 (73) xs5 b16 b15 b14 b13 b12 b11 b10 b9 (74) xs6 b24 b23 b22 b21 b20 b19 b18 b17 (75) xs7 a/c8 a7 a6 a5 a4 a3 a2 a/c1 (76) xs8 a/c16 a15 a14 a13 a12 a11 a10 a/c9 (77) xs9 a/c24 a23 a22 a21 a20 a19 a18 a/c17 (78) xs10 b/d8 b7 b6 b5 b4 b3 b2 b/d1 (79) xs11 b/d16 b15 b14 b13 b12 b11 b10 b/d9 (7a) xs12 b/d24 b23 b22 b21 b20 b19 b18 b/d17 (7b)
semiconductor group 264 11.96 peb 2254 operational description t1 6.1.2 status register address arrangement address write type comment 00 rfifo r receive fifo 4c frs0 r framer receive status 0 4d frs1 r framer receive status 1 4e frs2 r framer receive status 2 4f frs3 r framer receive status 3 50 fecl r framing error counter low 51 fech r framing error counter high 52 cvcl r code violation counter low 53 cvch r code violation counter high 54 cecl r crc error counter low 55 cech r crc error counter high 56 ebcl r errored block counter low 57 ebch r errored block counter high 58 59 5a 5b 5c rdl1 r receive dl-bit register 1 5d rdl2 r receive dl-bit register 2 5e rdl3 r receive dl-bit register 3 5f 60 61 62 test r manufacturer test register 63 test r manufacturer test register 64 sis r signaling status register 65 rsis r receive signaling status register 66 rbcl r receive byte control low 67 rbch r receive byte control high 68 isr0 r interrupt status register 0
semiconductor group 265 11.96 peb 2254 operational description t1 t1: status register address arrangement (contd) address write type comment 69 isr1 r interrupt status register 1 6a isr2 r interrupt status register 2 6b isr3 r interrupt status register 3 6c 6d 6e gis r global interrupt status 6f vstr r version status 70 rs1 r receive signaling register 1 71 rs2 r receive signaling register 2 72 rs3 r receive signaling register 3 73 rs4 r receive signaling register 4 74 rs5 r receive signaling register 5 75 rs6 r receive signaling register 6 76 rs7 r receive signaling register 7 77 rs8 r receive signaling register 8 78 rs9 r receive signaling register 9 79 rs10 r receive signaling register 10 7a rs11 r receive signaling register 11 7b rs12 r receive signaling register 12
semiconductor group 266 11.96 peb 2254 operational description t1 receive fifo (read) rfifo reading data from rfifo can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft1 ? 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the receive message complete command (rmc). framer receive status register 0 (read) los loss of signal (red alarm) detection: this bit is set when the incoming signal has ?no transitions (analog interface) or logical zeros (dig. interface) in a time interval of t consecutive pulses, where t is programmable via pcd register: total account of consecutive pulses: 1 6 semiconductor group 267 11.96 peb 2254 operational description t1 register pcr in the pcd time interval. digital interface: the bit will be reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) will be set. for additionally recovery conditions refer also to register lim2.los2/1. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4, 7 and no alarm condition exists. ais alarm indication signal (blue alarm) this bit is set when the conditions defined by bit fmr4.ais3 are detected. the flag stays active for at least one multiframe. with the rising edge of this bit an interrupt status bit (isr2.ais) will be set. it will be reset with the beginning of the next following multiframe if no alarm condition is detected. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4, 7 and no alarm condition exists. lfa loss of frame alignment the flag is set if pulseframe synchronization has been lost. the conditions are specified via bit fmr4.ssc1/0. setting this bit will cause an interrupt status (isr2.lfa). the flag is cleared when synchronization has been regained. additionally interrupt status isr2.far is set with clearing this bit. rra receive remote alarm (yellow alarm) the flag is set after detecting remote alarm (yellow alarm). conditions for setting/resetting are defined by bit rc1.rram. with the rising edge of this bit an interrupt status bit isr2.ra will be set. with the falling edge of this bit an interrupt status bit isr2.rar will be set. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4, 7 and no alarm condition exists.
semiconductor group 268 11.96 peb 2254 operational description t1 lmfa loss of multiframe alignment set in f12 or f72 format when 2 out of 4- (or 5 or 6) multiframe alignment patterns are incorrect. additionally the interrupt status bit isr2.lmfa is set. cleared after multiframe synchronization has been regained. with the falling edge of this bit an interrupt status bit isr2.mfar is generated. fsrf frame search restart flag toggles when no framing candidate (pulseframing or multiframing) is found and a new frame search is started. framer receive status register 1 (read) exzd excessive zeros detected significant only if excessive zeros detection is enabled (fmr2.exze=1). set after detecting of more than 7 (b8zs code) or more than 15 (ami code) contiguous zeros in the received bit stream. this bit is cleared when read. pden pulse density violation detected the pulse density of the received data stream is below the requirement defined by ansi t1. 403 or more than 15 consecutive zeros are detected. with the violation of the pulse density this bit will be set and will remain active until it is read. reading the register will clear this bit. (clear on read). additionally an interrupt status isr0.pden is generated with the rising edge of pden. llbdd line loop back deactuation signal detected this bit is set to one in case the llb deactuate signal 001 is detected and then received over a period of more than 33,16 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. 70 frs1 exzd pden llbdd llbad xls xlo (4d)
semiconductor group 269 11.96 peb 2254 operational description t1 llbad line loop back actuation signal detected this bit is set to one in case the llb actuate signal 00001 is detected and then received over a period of more than 33,16 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. xls transmit line short significant only if the ternary line interface is selected by lim1.drs=0. 0 normal operation. no short is detected. 1 the xl1 and xl2 are shortend for at least 32 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high impedance state if bit xpm2.daxlt is reset. after 32 consecutive pulse periods the outputs xl1/2 are activated again until the first pulse is transmitted. if a short between xl1/2 is still further active the outputs xl1/2 are in high impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit will be reset. with any change of this bit an interrupt isr1.xlsc will be generated. in case of xpm2.xlt is set this bit will be frozen. xlo transmit line open 0 normal operation 1 this bit will be set if at least 32 consecutive zeros were sent via pins xl1/xl2 resp. xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc will be set. in case of xpm2.xlt is set this bit will be frozen.
semiconductor group 270 11.96 peb 2254 operational description t1 framer receive status register 2 (read) esc2esc0 error simulation counter this three-bit counter is incremented by setting bit fmr0.sim. the state of the counter determines the function to be tested: for complete checking of the alarm indications, eight simulation steps are necessary (frs2.esc = 0 after a complete simulation). some of these alarm indications are simulated only if the falc54 is configured in the appropriate mode. at simulation steps 0, 3, 4, and 7 pending status flags are reset automatically and clearing of the error counters and interrupt status registers isr0-3 should be done. incrementing the simulation counter should not be done at time intervals shorter than 1.5 ms (f4, f12, f72) or 3 ms (esf). otherwise, reactions of initiated simulations may occur at later steps. 70 frs2 esc2 esc0 (4e) tested alarms esc2esc0 = 0 1 2 3 4 5 6 7 lfa x x lmfa x x rra (bit2 =0) x rra (s-bit fr. 12) x rra (dl-pattern) x los x x x ebc (f12,f72) x x ebc (only esf) x x x x ais xx xx fec x x cvc (only b8zs) x x x cec (only esf) x x x x slpp x slpn x xslp x x x x
semiconductor group 271 11.96 peb 2254 operational description t1 framer receive status register 3 (read) feh5feh0 f-bit error history the bits are set if errors occur in the corresponding framing bit locations. they will be updated once per superframe (esf format) or every six frames (other framing formats). organization: note: all error history bits corresponding to fs bits substituted by data link information are fixed to 0. 70 frs3 feh5 feh0 (4f) esf others feh5:fas(24) ft (6 or 12) feh4:fas(20) ft (5 or 11) feh3:fas(16) ft (4 or 10) feh2:fas(12) ft (3 or 9) feh1:fas(8) ft (2 or 8) feh0:fas(4) ft (1 or 7)
semiconductor group 272 11.96 peb 2254 operational description t1 framing error counter (read) fe15fe0 framing errors this 16-bit counter will be incremented when incorrect ft and fs bits in f4, f12 and f72 format or incorrect fas bits in esf format are received. framing errors will not be counted during asynchronous state. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter will be incremented twice. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dfec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe8 (51)
semiconductor group 273 11.96 peb 2254 operational description t1 code violation counter (read) cv15cv0 code violations no function if nrz code has been enabled. if the b8zs code (bit fmr0.rc1/0 = 11) is selected, the 16-bit counter will be incremented by detecting violations which are not due to zero substitution. if fmr2.exze is set, additionally excessive zero strings (more than 7 contiguous zeros) are detected and counted. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. if fmr2.exze is set, additionally excessive zero strings (more than 15 contiguous zeros) are detected and counted. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcvc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv8 (53)
semiconductor group 274 11.96 peb 2254 operational description t1 crc error counter (read) cr15cr0 crc errors no function if crc6 procedure or esf format are disabled. in esf mode, the 16-bit counter will be incremented when a multiframe has been received with a crc error. crc errors will not be counted during asynchronous state. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented once per multiframe. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cecl cr7 cr0 (54) 70 cech cr15 cr8 (55)
semiconductor group 275 11.96 peb 2254 operational description t1 errored block counter (read) ebc15ebc0 errored block counter in esf format this 16-bit counter will be incremented once per multiframe if a multiframe has been received with a crc error or an errored frame alignment has been detected. crc and framing errors will not be counted during asynchronous state. in f4/12/72 format an errored block contain 4/12 or 72 frames. incrementing is done once per multiframe if framing errors has been detected. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented in esf format once per multiframe and in f4/12/72 format only one time. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.debc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl ebc7 ebc0 (56) 70 ebch ebc15 ebc8 (57)
semiconductor group 276 11.96 peb 2254 operational description t1 receive dl-bit register 1 (read) rdl17rdl10receive dl-bit only valid if f12, f24 or f72 format is enabled. the received fs/dl-bits are shifted into this register. rdl10 is received in frame 1 and rdl17 in frame 15, if f24 format is enabled. rdl10 is received in frame 26 and rdl17 in frame 40, if f72 format is enabled. in f12 format the fs-bits of a complete multiframe is stored in this register. rdl10 is received in frame 2 and rdl15 in frame 12. this register will be updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 2 (read) rdl27rdl20receive dl-bit only valid if f24 or f72 format is enabled. the received dl-bits are shifted into this register. rdl20 is received in frame 17 and rdl23 in frame 23, if f24 format is enabled. rdl20 is received in frame 42 and rdl27 in frame 56, if f72 format is enabled. this register will be updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 3 (read) rdl37rdl30receive dl-bit only valid if f72 format is enabled. the received dl-bits are shifted into this register. rdl30 is received in frame 58 and rdl37 in frame 72, if f72 format is enabled. this register will be updated with every receive multiframe begin interrupt isr0.rmb. 70 rdl1 rdl17 rdl16 rdl15 rdl14 rdl13 rdl12 rdl11 rdl10 (5c) 70 rdl2 rdl27 rdl26 rdl25 rdl24 rdl23 rdl22 rdl21 rdl20 (5d) 70 rdl3 rdl37 rdl30 (5e)
semiconductor group 277 11.96 peb 2254 operational description t1 signaling status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres or C when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable data can be written to the xfifo. xrep transmission repeat status indication of cmdr.xrep. rli receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec command executing 0 ? no command is currently executed, the cmdr register can be written to. 1 ? a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 5 sclkx clock cycles if fmr1.imod=0 and 10 sclkx cycles if fmr1.imod is set. bom bit oriented message significant only in esf frame format and auto switching mode is enabled. 0 hdlc mode 1 bom mode 70 sis xdov xfw xrep rli cec bom (64)
semiconductor group 278 11.96 peb 2254 operational description t1 receive signaling status register (read) rsis relates to the last received hdlc or bom frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame determines whether a valid frame has been received. 1 ? valid 0 ? invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or C a frame which is too short taking into account the operation mode selected via mode (mds2-0) and the selection of receive crc on/off (ccr3.rcrc) as follows: ? mds2-0 = 011 (16 bit address), rcrc = 0 : 4 bytes; rcrc = 1 : 3-4 bytes ? mds2-0 = 010 (8 bit address), rcrc = 0 : 3 bytes; rcrc = 1 : 2-3 bytes note: shorter frames are not reported. rdo receive data overflow a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check 0 ? crc check failed; received frame contains errors. 1 ? crc check o.k.; received frame is error-free. rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. 70 rsis vfr rdo crc16 rab ha1 ha0 hfr la (65)
semiconductor group 279 11.96 peb 2254 operational description t1 ha1, ha0 high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the falc54 compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 00 rah2 has been recognized 01 broadcast address has been recognized 10 rah1 has been recognized c/r = 0(bit 1) 11 rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by 10or 11. hfr hdlc frame format 0 ? a bom frame was received. 1 ? a hdlc frame was received. note: rsis 7-2, 0 is not valid with a bom frame. la low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ? ral2 has been recognized 1 ? ral1 has been recognized receive byte count low (read) together with rbch (bits rbc11 - rbc8), indicates the length of a received frame (1 ? 4095 bytes). bits rbc4-0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. 70 rbcl rbc7 rbc0 (66)
semiconductor group 280 11.96 peb 2254 operational description t1 received byte count high (read) value after reset: 000 xxxxx ov counter overflow more than 4095 bytes received. rbc11 C rbc8 ? receive byte count (most significant bits) together with rbcl (bits rbc7 ? rbc0) indicate the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit ipc.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc4-0. additional information is available in the rsis register. rfs receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after a rfs interrupt, the contents of 70 rbch ov rbc11 rbc8 (67) 70 isr0 rme rfs isf rmb rsc crc6 pden rpf (68)
semiconductor group 281 11.96 peb 2254 operational description t1 ? ral1 ? rsis - bits 3-1 are valid and can be read by the cpu. isf incorrect sync format the falc54 could not detect eight consecutive ones within 32 bits in bom mode. only valid if bom receiver has been activated. rmb receive multiframe begin this bit is set with the beginning of a received multiframe of the receive line timing. rsc received signaling information changed this bit is set with the updating of a received signaling information in registers rs1-6 resp. rs1-12. if the last received signaling information changed from the previous received updating is started. this interrupt will only occur in the synchronous state. the registers rs1-6 /12 should be read within the next 1.5 / 3 ms otherwise the contents may be lost. crc6 receive crc6 error 0 no crc6 error occurs. 1 the crc6 check of the last received multiframe failed. pden pulse density violation the pulse density violation of the received data stream defined by ansi t1. 403 is violated. more than 15 consectuive zeros or less than n ones in each and every time window of 8(n+1) data bits (n=23) are detected. if ipc.sci is set high this interrupt status bit will be activated with every change of state of frs1.pden. rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. 70 isr1 case rdo alls xdu xmb xlsc xpr (69)
semiconductor group 282 11.96 peb 2254 operational description t1 if bit ipc.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. case transmit cas register empty in esf and f12 format this bit is set with the beginning of a transmitted multiframe related to the internal transmitter timing. in f72 format this interrupt will occur every 12 frames to inform the user that new bit robbing data has to written to xs1-6 registers. in esf format this interrupt will occur every 24 frames to write registers xs1-12. rdo receive data overflow this interrupt status indicates that the cpu does not respond quickly enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent this bit is set if the last bit of the current frame is completely sent out and xfifo is empty. xdu transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. xmb transmit multiframe begin this bit is set with the beginning of a transmitted multiframe related to the internal transmitter timing.
semiconductor group 283 11.96 peb 2254 operational description t1 xlsc transmit line status change xlsc is set to one with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit ipc.vis is set to 1, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached synchronization. set with the falling edge of bit fsr0.lfa. it is set also after alarm simulation is finished and the receiver is still synchron. lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it will be set during alarm simulation. mfar multiframe alignment recovery set when the framer has reached multiframe alignment in f12 or f72 format. with the negative transition of bit frs0.lmfa this bit will be set. it will be set during alarm simulation. 70 isr2 far lfa mfar lmfa ais los rar ra (6a)
semiconductor group 284 11.96 peb 2254 operational description t1 lmfa loss of multiframe alignment set when the framer has lost the multiframe alignment in f12 or f72 format. with the positive transition of bit frs0.lmfa this bit will be set. it will be set during alarm simulation. ais alarm indication signal (blue alarm) this bit is set when an alarm indication signal is detected and bit frs0.ais is set. if ipc.sci is set high this interrupt status bit will be activated with every change of state of frs0.ais. it will be set during alarm simulation. los loss of signal (red alarm) this bit is set when a loss of signal alarm is detected in the received data stream and frs0.los is set. if ipc.sci is set high this interrupt status bit will be activated with every change of state of frs0.los. it will be set during alarm simulation. rar remote alarm recovery set if a remote alarm (yellow alarm) is cleared and bit frs0.rra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm a remote alarm (yellow alarm) is detected. set with the rising edge of bit frs0.rra. it will be set during alarm simulation. interrupt status register 3 (read) all bits are reset when isr3 is read. if bit ipc.vis is set to 1, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. 7 0 isr3 es sec xslp llbsc sln slp (6b)
semiconductor group 285 11.96 peb 2254 operational description t1 es errored second this bit is set if at least one enabled interrupt source via imr4 is set during the time interval of one second. interrupt sources of imr4 register: lfa = loss of frame alignment detected fer = framing error received cer= crc error received ais = alarm indication signal (blue alarm) los = loss of signal (red alarm) cve = code violation detected slip= transmit slip or receive slip positive/negative detected sec second the internal one second timer has expired. the timer is derived from the internal 16 mhz clock. xslp transmit slip indication a one in this bit position indicates that there is an error in the host clock system. if the wander of the transmit route clock, which normally is phase locked to a common submultiple of the system clock (sclkx), is too great, data transmission errors will occur. in that case, the transmit speech memory has to be reset to its start position by writing the initial value to the transmit time-slot counter xc1.xto. llbsc line loop back status change this bit is set to one, if the llb actuate signal 00001 or the llb deactuate signal 001, resp., is detected over a period of 33,16 msec with a bit error rate less than 1/100. the llbsc bit is also set to one, if the current detection status is left, i.e., if the bit error rate exceeds 1/100. the actual detection status can be read from the frs1.llbad and frs1.llbdd, resp. sln slip negative the frequency of the receive route clock is greater than the frequency of sclkr. a frame will be skipped. it will be set during alarm simulation. slp slip positive the frequency of the receive route clock is less than the frequency of sclkr. a frame will be repeated. it will be set during alarm simulation.
semiconductor group 286 11.96 peb 2254 operational description t1 global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts (isr3isr0) version status register (read) vn3 C vn0 version number of chip 0 ? version 1.1 - 1.2 1 ? version 1.3 70 gis isr3 isr2 isr1 isr0 (6e) 70 vstr vn3 vn0 (6f)
semiconductor group 287 11.96 peb 2254 operational description t1 receive signaling register (read) value after reset: not defined receive signaling register 1-12 each register contains the received bit robbing information for 8 ds0 channels. the received robbed bit signaling information of a complete esf multiframe will be compared with the previously received one. in f12/72 frame format the received signaling information of every 12 frames will be compared with the previously received 12 frames. if the contents changed a receive signaling changed interrupt isr0.rsc is generated and informs the user that a new multiframe has to be read within the next 3 ms (esf) or 1.5 ms (f12/72). received data will be stored in rs1-12 (esf) and in rs1-6 (f12/72) registers. rs1.0 is received in channel 1 frame 1 and rs12.7 in channel 24 frame 24 (esf). if requests for reading the rs1-12 registers will be ignored the received data may be lost. 70 rs1 a8 a7 a6 a5 a4 a3 a2 a1 (70) rs2 a16 a15 a14 a13 a12 a11 a10 a9 (71) rs3 a24 a23 a22 a21 a20 a19 a18 a17 (72) rs4 b8 b7 b6 b5 b4 b3 b2 b1 (73) rs5 b16 b15 b14 b13 b12 b11 b10 b9 (74) rs6 b24 b23 b22 b21 b20 b19 b18 b17 (75) rs7 a/c8 a7 a6 a5 a4 a3 a2 a/c1 (76) rs8 a/c16 a15 a14 a13 a12 a11 a10 a/c9 (77) rs9 a/c24 a23 a22 a21 a20 a19 a18 a/c17 (78) rs10 b/d8 b7 b6 b5 b4 b3 b2 b/d1 (79) rs11 b/d16 b15 b14 b13 b12 b11 b10 b/d9 (7a) rs12 b/d24 b23 b22 b21 b20 b19 b18 b/d17 (7b)
peb 2254 electrical specification semiconductor group 288 11.96 7 electrical specification 7.1 absolute maximum ratings supply voltage v dd = C 0.3 to + 7.0 v input voltage v i = C 0.3 to v dd + 0.3 v (max. 7 v) output voltage v 0 = C 0.3 to v dd + 0.3 v (max. 7 v) storage temperature t stg = C 65 to + 150 c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied.
peb 2254 electrical specification semiconductor group 289 11.96 7.2 dc characteristics t a = C 40 to 85 ?c; v dd = 5 v 5 %, v ss = 0 v parameter symbol limit values unit test condition pins min. max. input low voltage v il C 0.4 0.8 v all pins except analog pins: rlx, xlx xtalx, xlxm, refr, tms, tdi input high voltage v ih 2.0 v dd + 0.4 v output low voltage v ol 0.45 v i ol = 2 ma output high voltage output high voltage v oh v oh 2.4 v dd C 0.5 v i oh = C 400 m a i oh = C 100 m a input leakage current output leakage current i li i lo 1 m a m a v in < v dd to 0 v 0 v < v out < v dd to 0 v input leakage current i tmsli 1 250 m a m a v in = v dd v in = 0 v tms, tdi input low voltage v xtalil C 0.4 1.0 v xtal1, xtal2, xtal3, xtal4 input high voltage v xtalih 4.0 v dd + 0.4 v input leakage current i xtali 15 m a0 v v in v dd to 0 v transmitter output impedance r x 0.3 w 3) xpm2.xlt=0 xl1, xl2 r x 6000 w 3) xpm2.xlt=1 transmitter output current i xe1 i xt1 60 75 ma ma note 1) note 2) depending on line length 1) wiring conditions and external circuit configuration according to figure 15; values of registers xpm2-0 = bd h , 03 h , 00 h . 2) wiring conditions and external circuit configuration according to figure 47; values of registers xpm2-0 = 9f h , 27 h , 02 h . 3) not tested in production.
peb 2254 electrical specification semiconductor group 290 11.96 peak voltage of a mark (cept) peak voltage of a mark (t1) v xcept v xt1 2.9 3.1 3.5 3.7 v v wired according to figure 15 wired according to figure 47 depending on line length; xl1, xl2 receiver input peak voltage of a mark v r 0.5 4.4 v receive input impedance 50 k w note 3) receiver input threshold v rth 45 % note 3) loss of signal threshold (differential input voltage between pins rl1/rl2) v los 1.36 1.04 0.84 0.62 0.43 0.32 0.22 not assigned v ril2-0 = 000 ril2-0 = 001 ril2-0 = 010 ril2-0 = 011 ril2-0 = 100 ril2-0 = 101 ril2-0 = 110 ril2-0 = 111 depends on programming of register lim1.ril2-0 (typical values) rl1, rl2 operational power supply current i cc 140 140 ma ma e1 application 1) , t1 application 2) , max value for all ones 1) wiring conditions and external circuit configuration according to figure 15; values of registers xpm2-0 = bd h , 03 h , 00 h . 2) wiring conditions and external circuit configuration according to figure 47; values of registers xpm2-0 = 9f h , 27 h , 02 h . 3) not tested in production. 7.2 dc characteristics (contd) t a = C 40 to 85 ?c; v dd = 5 v 5 %, v ss = 0 v
peb 2254 electrical specification semiconductor group 291 11.96 7.3 capacitances 7.4 recommended oscillator circuits figure 67 oscillator circuits the jitter attenuator requires unique performance specifications for the crystals. the following typical crystal parameters will meet this specifications: C motional capacitance c 1 = 25 ff min C shunt capacitance c 0 = 7 pf max C load capacitance c l = 15 pf typ C resonance resistance r r 20 w t a = 25 c; v dd = 5 v 5%, v ss = 0 v parameter symbol limit values unit pins typ. max. input capacitance 1) c in 5 10 pf all except xlxm, xtalx, refr output capacitance 1) c out 8 15 pf all except xlx, xtalx output capacitance 1) c out 8 20 pf xlx 1) not tested in production.
peb 2254 electrical specification semiconductor group 292 11.96 figure 68 dco1 tuning range (16.384 mhz crystal) crystal specified for c l = 15 pf) figure 69 dco2 tuning range (12.352 mhz crystal) crystal specified for c l = 15 pf
peb 2254 electrical specification semiconductor group 293 11.96 7.5 ac characteristics t a = C 40 to 85 ?c; v dd = 5 v 5 %, v ss = 0 v all inputs except rlx, xlxm, xtal1/3 are driven to v ih = 2.4 v for a logical 1 and to v il = 0.4 v for a logical 0 timing measurements except for xlx are made at v h = 2.0 v for a logical 1 and at v l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown below. figure 70 input/output waveform for ac tests
peb 2254 electrical specification semiconductor group 294 11.96 7.5.1 microprocessor interface 7.5.1.1 siemens/intel bus interface mode figure 71 siemens/intel non-multiplexed address timing figure 72 siemens/intel multiplexed address timing
peb 2254 electrical specification semiconductor group 295 11.96 figure 73 siemens/intel read cycle timing figure 74 siemens/intel write cycle timing
peb 2254 electrical specification semiconductor group 296 11.96 siemens/intel bus interface and interrupt timing no. parameter limit values unit min. max. 1 address, bhe setup time 15 ns 2 address, bhe hold time 0 ns 3 cs setup time 0 ns 3a cs hold time 0 ns 4 address, bhe stable before ale inactive 20 ns 5 address, bhe hold after ale inactive 10 ns 6 ale pulse width 30 ns 7 address latch setup time before cmd active 0 ns 7a ale to command inactive delay 30 ns 8 rd pulse width 100 ns 9 rd control interval 80 ns 10 data valid after rd active 95 ns 11 data hold after rd inactive 10 ns 11a rd inactive to data bus tristate 1) 50 ns 12 wr to rd or rd to wr control interval 80 ns 13 wr pulse width 60 ns 14 wr control interval 50 ns 15 data stable before wr inactive 30 ns 16 data hold after wr inactive 10 ns 1) not tested in production.
peb 2254 electrical specification semiconductor group 297 11.96 7.5.1.2 motorola bus interface mode figure 75 motorola read cycle timing figure 76 motorola write cycle timing
peb 2254 electrical specification semiconductor group 298 11.96 motorola bus interface timing no. parameter limit values unit min. max. 17 address, ble, setup time before ds active 15 ns 18 address, ble, hold after ds inactive 0 ns 19 cs active before ds active 0 ns 19a cs hold after ds inactive 0 ns 20 r w stable before ds active 10 ns 21 r w hold after ds inactive 0 ns 22 22a ds pulse width (read access) (write access) 100 60 ns ns 23 ds control interval 80 ns 24 data valid after ds active (read access) 95 ns 25 data hold after ds inactive (read access) 10 ns 25a ds inactive to databus tristate (read access) 1) 40 ns 26 data stable before ds active (write access) 30 ns 27 data hold after ds inactive (write access) 10 ns 1) not tested in production.
peb 2254 electrical specification semiconductor group 299 11.96 7.6 line interface 7.6.1 timing of dual rail and optical interface figure 77 timing of dual rail and optical interface
peb 2254 electrical specification semiconductor group 300 11.96 no. parameter limit values unit pcm 30 pcm 24 min. typ. max. min. max. 30 rclki clock period 488 648 ns 31 rclki clock period low 180 240 ns 32 rclki clock period high 180 240 ns 33 roid setup 50 50 ns 34 roid hold 50 50 ns 35 xclk clock period 488 648 ns 36 xclk clock period low xclk clock period low 4) 190 150 230 200 ns 37 xclk clock period high xclk clock period high 4) 190 150 230 200 ns 38 xoid delay 1) xdop/xdon delay 2) 50 50 ns 38a xoid delay 3) 50 ns 1) nrz coding 2) hdb3/ami coding 3) 1t2b coding 4) depends on input rclki in optical interface and remote loop without transmit jitter attenuator enabled (lim1.jatt/rl=01).
peb 2254 electrical specification semiconductor group 301 11.96 receive clock and rfsp/freezs timing figure 78 receive clock and rfsp/freezs timing no. parameter limit values unit pcm 30 pcm 24 min. typ. max. min. typ. max. 39 rclk clock period 488 648 ns 40 rclk clock period low 180 240 ns 41 rclk clock period high 180 240 ns 42 rfsp delay 70 70 ns 43 freezs delay 1) 95 95 ns 1) only in pcm24 mode and if bit xco.sfrz is set high. in pcm30 mode and if bit fmr3.cfrz is set high.
peb 2254 electrical specification semiconductor group 302 11.96 7.7 system clocks figure 79 timing of the system clock interface
peb 2254 electrical specification semiconductor group 303 11.96 system clock interface timing parameter values no. parameter limit values unit min. typ. max. 44 clk16m period 16 mhz 61 ns 45 clk16m period 16 mhz low 20 ns 46 clk16m period 16 mhz high 20 ns 47 clk8m period 8 mhz 122 ns 48 clk8m period 8 mhz low 45 ns 49 clk8m period 8 mhz high 45 ns 50 clkx period 4 mhz 244 ns 51 clkx period 4 mhz low 100 ns 52 clkx period 4 mhz high 100 ns 53 clkx period 2mhz 488 ns 54 clkx period 2 mhz low 220 ns 55 clkx period 2 mhz high 220 ns 56 fsc , fsc, clk8m, clkx delay 50 ns 57 clk12m period 12 mhz 81 58 clk12m period 12 mhz low 25 ns 59 clk12m period 12 mhz high 25 ns
peb 2254 electrical specification semiconductor group 304 11.96 xtal timing figure 80 timing of xtal1/xtal3 xtal1/xtal3 timing parameter values no. parameter limit values unit condition min. typ. max. 61 clock period of crystal/clock 61 81 ns xtal1/3 xtal3 62 high phase of crystal/clock 25 33 ns xtal1/3 xtal3 63 low phase of crystal/clock 25 33 ns xtal1/3 xtal3
peb 2254 electrical specification semiconductor group 305 11.96 7.8 system interface figure 81 system interface timing
peb 2254 electrical specification semiconductor group 306 11.96 figure 82 xmfs-timing
peb 2254 electrical specification semiconductor group 307 11.96 system interface timing no. parameter limit values unit 8192 khz sclk min. typ. max. 65 sclkx/sclkr period 8 mhz 122 ns 66 sclkx/sclkr period 8 mhz low 40 ns 67 sclkx/sclkr period 8 mhz high 40 ns 68 sypx/ sypr inactive setup time 1) 2 t 65 ns 69 sypx/ sypr setup time 5 ns 70 sypx/ sypr hold time 55 ns 71 rdo delay 10 1) 105 ns 71a rdo to high impedance 1) (fmr1.imod = 0) 10 105 ns 72 rsigm, rmfb, dlr marker delay 105 ns 73 xdi setup 5 ns 74 xdi hold 55 ns 75 xsigm, xmfb, dlx marker delay 105 ns 76 xclk delay 105 ns 77 xmfs setup time 5 ns 78 xmfs pulse width 2 t 65 ns 79 xmfs inactive setup time 1) 4 t 65 ns 1) not tested in production.
peb 2254 electrical specification semiconductor group 308 11.96 7.9 jtag boundary scan timing figure 83 jtag boundary scan timing no. parameter limit values unit min. max. 80 tck period 250 ns 81 tck high time 80 ns 82 tck low time 80 ns 83 tms setup time 40 ns 84 tms hold time 40 ns 85 tdi setup time 40 ns 86 tdi hold time 40 ns 87 tdo valid delay 100 ns
peb 2254 electrical specification semiconductor group 309 11.96 reset timing figure 84 reset timing no. parameter limit values unit min. max. 88 res pulse width 20000 ns
peb 2254 electrical specification semiconductor group 310 11.96 7.10 pulse templates - transmitter the falc54 meets both itu-t and t1 pulse template requirements. figure 85 pulse template at the transmitter ouput for cept applications
peb 2254 electrical specification semiconductor group 311 11.96 figure 86 t1 pulse shape at the cross connect point table 26 t1 pulse template corner points at the cross connect point (t1.i102) 100 % value must be in the range between 2.4 v and 3.6 v. maximum curve time [ns] v [%] minimum curve time [ns] v [%] ( 0, 0.05) ( 250, 0.05) ( 325, 0.80) ( 325, 1.15) ( 425, 1.15) ( 500, 1.05) ( 675, 1.05) ( 725, -0.07) ( 1100, 0.05) ( 1250, 0.05) ( 0, -0.05) ( 350, -0.05) ( 350, 0.5) ( 400, 0.95) ( 500, 0.95) ( 600, 0.90) ( 650, 0.50) ( 650, -0.45) ( 800, -0.45) ( 925, -0.2) ( 1100, -0.05) ( 1250, -0.05)
peb 2254 electrical specification semiconductor group 312 11.96 figure 87 pulse shape according to itu-t g.703
peb 2254 package outlines semiconductor group 313 11.96 8 package outlines p-mqfp-80-1 (plastic metric quad flat package) gpm05249 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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